Automatic creation of vias in electrical circuit design

• US 8,086,991 B1
• Filed: 07/25/2008
• Issued: 12/27/2011
• Est. Priority Date: 07/25/2007
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: AWR Corporation
• Inventors: Pekarek, Joseph Edward
• Primary Examiner(s): Whitmore, Stacy
• Application Number:
  US12/220,508
• Time in Patent Office: 1,250 Days
• Field of Search: 716 10- 15, 716 30-139
• US Class Current: 716/137
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

This invention is directed to a methodology of creating and detecting crossings of conductive traces on different layers of an integrated circuit or a conducting trace over a device contact during a system. Values are stored by the system simulator corresponding to the galvanic potential or same “net,” and then by a set of rule based instructions the vias are automatically displayed, correct-by-construction, and via connections between the traces, or the trace and device contact, to short circuit the paths. The via structure will not be created if it will short-circuit a conducting trace not associated with the net in question. By connecting traces on different layers using automatically created via structures so as not to short circuit other net traces, errors are eliminated and design cycles reduced when compared to a manual design scheme of inserting via connections. There is a number of useful variations that can be applied to the via structure automatically created. There is also an interactive mode which allows the via to be easily resized by the use of familiar control handles.

Claims

1. A computer-implemented method of a circuit design, comprising:

determining an overlap area between at least two circuit components where the at least two circuit components are part of a same net; and

automatically inserting a conducting via in the overlap area between the at least two circuit components because the circuit design implicitly knows that the at least two circuit components are connected to the same net.

2. The method of claim 1, where the automatically inserting the conducting via is constrained by the size of the at least two circuit components.

3. The method of claim 1, where the circuit components further comprise metallization layers.

4. The method of claim 1, where the circuit components further comprise device pins.

5. The method of claim 1, where the conducting via size can be reshaped by user control handles.

6. The method of claim 1, further comprising creating the conducting via size by limiting the via structure to the overlap area of the circuit component with the conducting via.

7. The method of claim 1, further comprising creating the conducting via size by extending the conducting via to extend beyond the overlap area of the at least two circuit components with the conducting via.

8. The method of claim 1, further comprising creating a via cap structure capable of supporting a plurality of the conducting vias.

9. The method of claim 1, further comprising creating the conducting via size by encompassing an area bounded by overlapping the at least two circuit components with the conducting via.

10. The method of claim 1, where the automatically insertion of the connecting via is created between a first metal trace located on a first layer and a second metal trace located on a second layer.

11. The method of claim 10, where the automatically insertion of the connecting via has a wider width than the first and second metal traces.

12. The method of claim 1, further comprising creating user defined construction constraints limiting the conducting via size.

13. A method comprising:

assessing, by operation of a computer, a circuit design comprising;

determining an overlap area between at least two circuit components where the at least two circuit components are part of a same net and have no other circuit components connected to a different net located in the overlap area between the at least two circuit components; and

automatically inserting a conducting via structure further comprising a plurality of vias and a via cap in the overlap area between the at least two circuit components because the circuit design implicitly knows that the at least two circuit components are connected to the same net based on user defined design rules.

14. The method of claim 13, where the automatically inserting the conducting via cap is larger in cross sectional area than the plurality of vias.

15. The method of claim 13, further comprising creating a layout for a circuit board where the automatically inserting the conducting via structure electrically connects at least two circuit layers.

16. The method of claim 13, further comprising resizing the conducting via structure by the manual use of control handles located on the conducting via structure.

17. The method of claim 13, further comprising creating the conducting via structure size by limiting the conducting via structure to the overlap area of the at least two circuit components with the conducting via structure.

18. The method of claim 13, further comprising creating the via size by extending the conducting via structure to beyond the overlap area of the at least two circuit components with the conducting via structure.

19. The method of claim 13, further comprising creating the conducting via size by encompassing an area bounded by the overlap area of a pin with the conducting via structure.

20. The method of claim 13, further comprising creating the conducting via structure in the shape of a polygon.

21. The method of claim 20, further comprising resizing the conducting via structure by a control handle operable by manual manipulation of the conducting via structure size.

22. The method of claim 21, further comprising implementing construction constraints to limit the conducting via structure size.

23. The method of claim 13, further comprising designing metallic conducting traces based on a printed circuit board design stored in the memory of the computer.

24. A computer-readable medium storing instructions operable when executed by a computer, comprising:

determining whether a plurality of metallic conducting traces overlap between layers on a circuit design that are part of a same net and have no other net traces in between the overlap of the conducting traces;

determining whether a conducting via can be automatically created in the overlap between the plurality of metallic conducting traces that are part of the same net if there is no other traces representing a different net in the overlap between the metallic traces representing the same net; and

automatically inserting at least one a conducting via in the overlap between the plurality of metallic conducting traces that are part of the same net because the circuit design implicitly knows that the plurality of metal traces are connected to the same net.

25. The computer-readable medium storing instructions operable when executed by a computer, of claim 24 further comprising resizing the conducting via by the use of manually operated control handles.