Method of manufacturing a semiconductor device including a superlattice strain relief layer

• US 8,088,637 B1
• Filed: 05/04/2009
• Issued: 01/03/2012
• Est. Priority Date: 11/14/2005
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Palo Alto Research Center, Inc. (Xerox Holdings Corp.)
• Inventors: Wong, William S., Yang, Zhihong, Teepe, Mark, Knollenberg, Cliff, Kneissl, Michael A.
• Primary Examiner(s): REAMES, MATTHEW L
• Application Number:
  US12/435,333
• Time in Patent Office: 974 Days
• Field of Search: 438/47, 257/E33.008
• US Class Current: 438/47
• CPC Class Codes: B82Y 20/00 Nanooptics, e.g. quantum optics or photonic crystals
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 33/04 with a quantum effect structure or superlattice, e.g. tunnel junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01S 5/0213 Sapphire, quartz or diamond based substrates
• CPC Class Codes: H01S 5/0216 using an intermediate compound, e.g. a glue or solder
• CPC Class Codes: H01S 5/0217 Removal of the substrate
• CPC Class Codes: H01S 5/0234 Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings
• CPC Class Codes: H01S 5/34333 with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser

Abstract

A GaN/AlN superlattice is formed over a GaN/sapphire template structure, serving in part as a strain relief layer for growth of subsequent layers (e.g., deep UV light emitting diodes). The GaN/AlN superlattice mitigates the strain between a GaN/sapphire template and a multiple quantum well heterostructure active region, allowing the use of high Al mole fraction in the active region, and therefore emission in the deep UV wavelengths.

Claims

1. A method of manufacturing a semiconductor light emitting diode comprising the steps of:

forming over and in contact with a substrate a GaN template layer;

forming over and in contact with said GaN template layer a superlattice structure, said superlattice structure comprising a plurality of layer pairs, a first layer of said layer pairs being AlN and a second layer of said layer pairs being GaN;

forming over said superlattice structure a multiple quantum well heterostructure of a composition including at least 25% aluminum;

forming a contact layer over said multiple quantum well heterostructure;

securing a planar heat sink body to said contact layer; and

thereafter removing said substrate and said GaN template layer;

whereby said semiconductor light emitting diode may emit light generally perpendicularly to the plane of the heat sink body.

2. The method of manufacturing a semiconductor light emitting diode of claim 1, further comprising the step of removing said superlattice structure.

3. A method of manufacturing a semiconductor light emitting diode comprising the steps of:

forming over and in contact with a substrate a GaN template layer;

forming over and in contact with said GaN template layer a superlattice structure, said superlattice structure comprising a plurality of layer pairs, a first layer of said layer pairs being AlN and a second layer of said layer pairs being GaN;

forming over said superlattice structure a multiple quantum well heterostructure of a composition including at least 25% aluminum;

forming a contact layer over said multiple quantum well heterostructure;

securing a transfer substrate to said contact layer;

removing said substrate and said GaN template layer;

securing said semiconductor light emitting diode to a planar heat sink body at a surface opposite said transfer substrate; and

removing said transfer substrate from said semiconductor light emitting diode;

whereby said semiconductor light emitting diode may emit light generally perpendicularly to the plane of the heat sink body.

4. The method of manufacturing a semiconductor light emitting diode of claim 3, further comprising the step of removing said superlattice structure.