Selective etch chemistries for forming high aspect ratio features and associated structures
First Claim
1. A method for integrated circuit fabrication, comprising:
- providing an interlevel dielectric (ILD) layer overlying a substrate;
providing a masking layer overlying the ILD layer, the masking layer having an opening exposing the ILD layer;
forming a hole in the ILD layer by etching into the opening, wherein forming the hole comprises;
initially etching exposed parts of the ILD layer with plasma-excited species generated from a carbon compound without contacting the exposed parts to plasma-excited silicon species; and
subsequently etching exposed parts of the ILD layer with both plasma-excited species generated from a silicon compound and plasma-excited species generated from the carbon compound.
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Abstract
An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x≧1, y≧0 and z≧0. The carbon species can be generated from a carbon compound, such as CαMβHγ, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and α≧1, β≧0 and γ≧0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.
97 Citations
20 Claims
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1. A method for integrated circuit fabrication, comprising:
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providing an interlevel dielectric (ILD) layer overlying a substrate; providing a masking layer overlying the ILD layer, the masking layer having an opening exposing the ILD layer; forming a hole in the ILD layer by etching into the opening, wherein forming the hole comprises; initially etching exposed parts of the ILD layer with plasma-excited species generated from a carbon compound without contacting the exposed parts to plasma-excited silicon species; and subsequently etching exposed parts of the ILD layer with both plasma-excited species generated from a silicon compound and plasma-excited species generated from the carbon compound. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for semiconductor processing, comprising:
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providing a silicon-containing dielectric layer; and etching openings in the dielectric layer, wherein etching the openings in the dielectric layer comprises; initially etching exposed surfaces of the dielectric layer with plasma-excited species generated from a carbon compound; and subsequently increasing a depth of the openings while contacting exposed surfaces of the openings to plasma-excited species generated from a silicon compound, wherein initially etching exposed surfaces of the dielectric layer is performed without contacting the exposed surface with the plasma-excited species generated from the silicon compound. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification