Thin film transistor array panel and manufacturing method thereof

• US 8,089,072 B2
• Filed: 05/26/2010
• Issued: 01/03/2012
• Est. Priority Date: 07/27/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong-Gyu
• Primary Examiner(s): Such, Matthew W
• Application Number:
  US12/788,163
• Publication Number:
  US 20110233551A1
• Time in Patent Office: 587 Days
• Field of Search: 257/57, 257/72, 257/E27.111, 257/E29.273, 438/158
• US Class Current: 257/72
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; forming a gate insulating layer on the gate line; forming a semiconductor layer on the gate insulating layer; forming an ohmic contact on the semiconductor layer; forming a data line and a drain electrode on the ohmic contact; depositing a passivation layer on the data line and the drain electrode; forming a first photoresist layer on the passivation layer; etching the passivation layer and the gate insulating layer using the first photoresist layer as a mask to expose a portion of the drain electrode and a portion of the substrate; depositing a conductive film; and removing the photoresist layer; to form a pixel electrode on a portion of the drain electrode exposed by the etching of the passivation layer.

Claims

1. A thin film transistor array panel comprising:

a gate line formed on a substrate;

a gate insulating layer formed on the gate line;

a semiconductor layer formed on the gate insulating layer;

a data line and a drain electrode formed on the semiconductor layer, the drain electrode including first and second portions;

a passivation layer formed on the data line and the first portion of the drain electrode; and

a pixel electrode formed on the substrate and the second portion of the drain electrode, said pixel electrode having edges substantially coinciding with edges of the passivation layer;

wherein the gate insulating layer has edges substantially coinciding with edges of the passivation layer except for a portion around the drain electrode,

an upper surface of the portion of the gate insulating layer around the drain electrode is exposed, and

the exposed upper surface of the gate insulating layer is covered with the pixel electrode.

2. The thin film transistor array panel of claim 1, wherein:

the passivation layer has a contact hole exposing a portion of the data line; and

the thin film transistor array panel further comprises a contact assistant formed in the contact hole and having edges substantially coinciding with edges of the contact hole.

3. The thin film transistor array panel of claim 1, wherein the gate insulating layer has edges substantially coinciding with edges of the passivation layer except for a portion under the drain electrode.

4. The thin film transistor array panel of claim 1, wherein the semiconductor layer has substantially the same planar shape as the data line and the drain electrode except for a portion disposed between the data line and the drain electrode.

5. The thin film transistor array panel of claim 1, wherein the pixel electrode includes a cutout.

6. The thin film transistor array panel of claim 5, further comprising a storage electrode comprised of the same layer as the gate line and overlapping the pixel electrode.

7. The thin film transistor array panel of claim 6, further comprising a storage conductor formed on the gate insulating layer, connected to the pixel electrode, and overlapping the storage electrode.