High performance system-on-chip discrete components using post passivation process

• US 8,089,155 B2
• Filed: 02/18/2005
• Issued: 01/03/2012
• Est. Priority Date: 12/21/1998
• Status: Expired due to Term

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megica Corporation (Chipbond Technology Corporation)
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Ha, Nathan W
• Application Number:
  US11/062,276
• Publication Number:
  US 20050230783A1
• Time in Patent Office: 2,510 Days
• Field of Search: 257/758, 257/760, 257/774, 257/E23.141, 257/E23.142, 257/E23.145, 257/734, 257/737
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03914 the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05082 Two-layer arrangements
• CPC Class Codes: H01L 2224/05083 Three-layer arrangements
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1132 : Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1146 : Plating
• CPC Class Codes: H01L 2224/11849 : Reflowing
• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16265 : the item being a discrete passive component
• CPC Class Codes: H01L 2224/29124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/29144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/29147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/29155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/29166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/29171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/45124 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 23/3192 : Multilayer coating
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5222 : Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5223 : Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5227 : Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 : Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5286 : Arrangements of power or ground buses
• CPC Class Codes: H01L 23/5329 : Insulating materials
• CPC Class Codes: H01L 23/60 : Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 23/642 : Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 : Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/647 : Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 27/0676 : comprising combinations of diodes, or capacitors or resistors
• CPC Class Codes: H01L 27/08 : including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01038 : Strontium [Sr]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1423 : Monolithic Microwave Integrated Circuit [MMIC]
• CPC Class Codes: H01L 2924/15174 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Claims

1. An integrated circuit chip comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a passivation layer over said first metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening;

a polymer layer on said passivation layer, wherein said polymer layer has a thickness between 2 and 150 micrometers, wherein a second opening in said polymer layer is over said first contact point;

a passive device over said polymer layer and vertically over said first contact point;

a second metallization structure on said first contact point, wherein said second metallization structure comprises a glue layer, a copper-containing seed layer on said glue/barrier layer, and an electroplated copper layer on said copper-containing seed layer; and

a solder between said first contact point and said passive device and over said second metallization structure, wherein said passive device is connected to said first contact point through said solder and said second metallization structure.

2. The integrated circuit chip of claim 1, wherein said polymer layer comprises polyimide.

3. The integrated circuit chip of claim 1, wherein said passive device comprises a capacitor.

4. The integrated circuit chip of claim 1, wherein said passive device comprises an inductor.

5. The integrated circuit chip of claim 1, wherein said passive device comprises a resistor.

6. The integrated circuit chip of claim 1 further comprising a second metal interconnect over said silicon substrate, wherein a third opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said third opening pad, wherein a fourth opening in said polymer layer is over said second contact point, wherein said passive device is connected to said second contact point through said fourth opening, wherein said passive device is further vertically over said second contact point.

7. The integrated circuit chip of claim 1, wherein said glue layer comprises a titanium-containing layer.

8. The integrated circuit chip of claim 1, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.

9. The integrated circuit chip of claim 1, wherein said passivation layer comprises a nitride layer.

10. The integrated circuit chip of claim 1, wherein said silicon substrate has a portion not vertically under said passive device.

11. The integrated circuit chip of claim 1, wherein said passive device is a discrete passive device.

12. An integrated circuit chip comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a passivation layer over said first metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening;

a second metallization structure connected to said first contact point through said first opening, wherein said second metallization structure comprises a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer, and an electroplated nickel layer on said electroplated copper layer;

a passive device over said silicon substrate; and

a solder between said second metallization structure and said passive device, wherein said passive device is connected to said second metallization structure through said solder.

13. The integrated circuit chip of claim 12 further comprising a polymer layer between said passivation layer and said passive device.

14. The integrated circuit chip of claim 13, wherein said polymer layer comprises polyimide.

15. The integrated circuit chip of claim 13, wherein said polymer layer has a thickness between 2 and 150 micrometers.

16. The integrated circuit chip of claim 12, wherein said passive device comprises a capacitor.

17. The integrated circuit chip of claim 12, wherein said passive device comprises an inductor.

18. The integrated circuit chip of claim 12, wherein said passive device comprises a resistor.

19. The integrated circuit chip of claim 12, wherein said passive device is further vertically over said first contact point.

20. The integrated circuit chip of claim 19 further comprising a second metal interconnect over said silicon substrate, wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said passive device is connected to said second contact point through said second opening.

21. The integrated circuit chip of claim 12, wherein said glue layer comprises a titanium-containing layer.

22. The integrated circuit chip of claim 12, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.

23. The integrated circuit chip of claim 12, wherein said passivation layer comprises a nitride layer.

24. The integrated circuit chip of claim 12, wherein said silicon substrate has a portion not vertically under said passive device.

25. The integrated circuit chip of claim 12, wherein said passive device is a discrete passive device.

34. The integrated circuit chip of claim 22, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.

35. The integrated circuit chip of claim 22, wherein said passivation layer comprises a nitride layer.

26. An integrated circuit chip comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate;

a passivation layer over said first metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contract point is at a bottom of said second opening;

a polymer layer on said passivation layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point;

a passive device over said passivation layer and over said polymer layer, wherein said passive device has a first terminal connected to said first contact point through said third opening, and a second terminal connected to said second contact point through said fourth opening;

a second metallization structure connected to said first contact point through said third opening, wherein said second metallization structure comprises a glue layer, a copper-containing seed layer on said glue layer, and an electroplated copper layer on said copper-containing seed layer; and

a solder between said first terminal and said second metallization structure, wherein said first terminal is connected to said first contact point through said solder and said second metallization structure.

27. The integrated circuit chip of claim 26, wherein said polymer layer comprises polyimide.

28. The integrated circuit chip of claim 26, wherein said polymer layer has a thickness between 2 and 150 micrometers.

29. The integrated circuit chip of claim 26, wherein said passive device comprises a capacitor.

30. The integrated circuit chip of claim 26, wherein said passive device comprises an inductor.

31. The integrated circuit chip of claim 26, wherein said passive device comprises a resistor.

32. The integrated circuit chip of claim 26, wherein said second metallization structure further comprises a nickel-containing layer on said electroplated copper layer.

33. The integrated circuit chip of claim 26, wherein said glue layer comprises a titanium-containing layer.

36. The integrated circuit chip of claim 26, wherein said silicon substrate has a portion not vertically under said passive device.

37. The integrated circuit chip of claim 26, wherein said passive device is a discrete passive device.

38. An integrated circuit chip comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a first metallization structure over said silicon substrate, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate;

a passivation layer over said first metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said passivation layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening;

a passive device over said passivation layer, wherein said passive device has a first terminal connected to said first contact point through said first opening, and a second terminal connected to said second contact point through said second opening;

a second metallization structure connected to said first contact point through said first opening, wherein said second metallization structure comprises a glue layer, a copper-containing seed layer on said glue layer, an electroplated copper layer on said copper-containing seed layer, and a nickel-containing layer on said electroplated copper layer; and

a solder between said first terminal and said second metallization structure, wherein said first terminal is connected to said first contact point through said solder and said second metallization structure.

39. The integrated circuit chip of claim 38, wherein said passivation layer comprises a nitride layer.

40. The integrated circuit chip of claim 38, wherein said passive device comprises a capacitor.

41. The integrated circuit chip of claim 38, wherein said passive device comprises an inductor.

42. The integrated circuit chip of claim 38, wherein said passive device comprises a resistor.

43. The integrated circuit chip of claim 38, wherein said glue layer comprises a titanium-containing layer.

44. The integrated circuit chip of claim 38, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.

45. The integrated circuit chip of claim 38, wherein said silicon substrate has a portion not vertically under said passive device.

46. The integrated circuit chip of claim 38, wherein said passive device is a discrete passive device.

47. A circuit component comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a metal interconnect over said silicon substrate;

a separating layer over said metallization structure and over said dielectric layer, wherein a first opening in said separating layer is over a contact point of said metal interconnect, and said contact point is at a bottom of said first opening, wherein said separating layer comprises a nitride layer;

a polymer layer on said separating layer, wherein a second opening in said polymer layer is over said contact point;

a metal bump on said contact point and on said polymer layer, wherein said metal bump is connected to said contact point through said second opening, wherein said metal bump comprises a bottom portion comprising a glue layer, a copper-containing seed layer on said glue layer, and an electroplated copper layer on said copper-containing seed layer, and a top portion comprising a solder joint over said bottom portion of said metal bump; and

a passive device over said polymer layer and over said top portion of said metal bump, wherein said passive device is connected to said contact point through said metal bump, wherein said silicon substrate has a portion not vertically under said passive device.

48. The circuit component of claim 47, wherein said polymer layer comprises polyimide.

49. The circuit component of claim 47, wherein said polymer layer has a thickness between 2 and 150 micrometers.

50. The circuit component of claim 47, wherein said passive device comprises a capacitor.

51. The circuit component of claim 47, wherein said passive device comprises an inductor.

52. The circuit component of claim 47, wherein said passive device comprises a resistor.

53. The circuit component of claim 47, wherein said bottom portion of said metal bump further comprises a nickel-containing layer on said electroplated copper layer.

54. The circuit component of claim 47, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.

55. The circuit component of claim 47, wherein said passive device is a discrete passive device.

56. A circuit component comprising:

a silicon substrate;

a transistor in and on said silicon substrate;

a metallization structure over said silicon substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer;

a dielectric layer between said first and second metal layers;

a first metal interconnect over said silicon substrate;

a second metal interconnect over said silicon substrate;

a separating layer over said metallization structure and over said dielectric layer, wherein a first opening in said separating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, and wherein a second opening in said separating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, wherein said separating layer comprises a nitride layer;

a polymer layer on said separating layer, wherein a third opening in said polymer layer is over said first contact point, and a fourth opening in said polymer layer is over said second contact point;

a first metal bump on said first contact point and on said polymer layer, wherein said first metal bump is connected to said first contact point through said third opening, wherein said first metal bump comprises a bottom portion comprising a glue layer, a copper-containing seed layer on said glue layer, and an electroplated copper layer on said copper-containing seed layer, and a top portion comprising a solder joint over said bottom portion;

a second metal bump on said second contact point and on said polymer layer, wherein said second metal bump is connected to said second contact point through said fourth opening; and

a discrete passive device over said polymer layer and over said first and second metal bumps.

57. The circuit component of claim 56, wherein said glue layer comprises titanium.

58. The circuit component of claim 56, wherein said polymer layer has a thickness between 2 and 150 micrometers.

59. The circuit component of claim 56, wherein said discrete passive device comprises a capacitor.

60. The circuit component of claim 56, wherein said discrete passive device comprises an inductor.

61. The circuit component of claim 56, wherein said discrete passive device comprises a resistor.

62. The circuit component of claim 56, wherein said bottom portion of said first metal bump further comprises a nickel-containing layer on said electroplated copper layer.

63. The circuit component of claim 56, wherein said electroplated copper layer has a thickness between 3 and 20 micrometers.