Semiconductor package with increased I/O density and method of making the same

• US 8,089,159 B1
• Filed: 10/03/2007
• Issued: 01/03/2012
• Est. Priority Date: 10/03/2007
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Park, Doo Hyun, Kim, Jae Yoon, Jung, Yoon Ha
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): CHOI, CALVIN Y
• Application Number:
  US11/866,886
• Time in Patent Office: 1,553 Days
• Field of Search: 257666-733, 257/735, 257/773, 257/786, 438106-127, 438611-617
• US Class Current: 257/773
• CPC Class Codes: H01L 21/4832 Etching a temporary substrate after encapsulation process to form leads
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/16245 the item being metallic
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/78 : Apparatus for connecting with wire connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/838 : Bonding techniques
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/85001 : involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49582 : Metallic layers on lead frames
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

The present invention is related to a semiconductor package and method for fabricating the same wherein the semiconductor package includes a die pad having a semiconductor die mounted thereto, and two or more sets of leads or I/O pads which extend at least partially about the die pad in spaced relation thereto and to each other. The formation of the die pad and the leads of the leadframe are facilitated by the completion of multiple plating and chemical etching processes in a prescribed sequence. The present invention is further related to a semiconductor package and method for fabricating the same wherein the semiconductor package includes a semiconductor die electrically connected a plurality of leads or I/O pads via a flip chip type connection, each of the leads being formed by the completion of multiple plating and chemical etching processes in a prescribed sequence.

Claims

1. A semiconductor package, comprising:

a die pad having opposed first and second pad surfaces, and a third pad surface extending between the first and second pad surfaces;

a conductive ring having opposed first and second ring surfaces, and a third ring surface extending between the first and second ring surfaces;

a plurality of I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the I/O pads being segregated into at least an inner set which extends at least partially about the conductive ring and an outer set which extends at least partially about the inner set, the third surface of each of the I/O pads being inclined such that the first surface is of a first area and the second surface is of a second area which exceeds the first area, the first surface of each of the I/O pads further defining a peripheral edge and including a first plated layer which is formed thereon and protrudes beyond the peripheral edge;

at least one semiconductor die attached to the first pad surface of the die pad and electrically connected to the die pad, the conductive ring and at least one of the I/O pads; and

a package body at least partially encapsulating the die pad, the conductive ring, the I/O pads and the semiconductor die such that at least the second pad surface of the die pad, the second ring surface of the conductive ring and the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.

2. The semiconductor package of claim 1 wherein:

the first pad surface of the die pad defines a peripheral edge and includes a first plated pad layer formed thereon; and

the first plated pad layer protrudes beyond the peripheral edge of the first pad surface.

3. The semiconductor package of claim 2 wherein the third pad surface of the die pad is inclined such that the first pad surface is of a first area and the second pad surface is of a second area which exceeds the first area.

4. The semiconductor package of claim 1 wherein the second pad surface of the die pad includes a second plated pad layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body.

5. The semiconductor package of claim 1 wherein:

the first ring surface of the conductive ring defines inner and outer peripheral edges and includes a first plated ring layer formed thereon; and

the first plated ring layer protrudes beyond the inner and outer peripheral edges of the first ring surface.

6. The semiconductor package of claim 5 wherein the third ring surface of the conductive ring is inclined such that the first ring surface is of a first area and the second ring surface is of a second area which exceeds the first area.

7. The semiconductor package of claim 1 wherein the second ring surface of the conductive ring includes a second plated ring layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body.

8. The semiconductor package of claim 1 wherein the second surface of each of the I/O pads includes a second plated layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body.

9. The semiconductor package of claim 1 wherein the semiconductor die is electrically connected to the die pad, the conductive ring anti each of the I/O pads by conductive wires which are covered by the package body.

10. A semiconductor package, comprising:

a plurality or I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the first surface of each of the I/O pads defining a peripheral edge and including a first plated layer formed thereon which protrudes beyond the peripheral edge of the first surface, the third surface of each of the I/O pads being inclined such that the first surface is of a first area and the second surface is of a second area which exceeds the first area;

at least one semiconductor die electrically connected to each of the I/O pads; and

a package body at least partially encapsulating the I/O pads and the semiconductor die such that at least the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.

11. The semiconductor package of claim 10 wherein the at least one semiconductor die is electrically connected to the I/O pads by conductive wires which are covered by the package body.

12. A semiconductor package, comprising:

a die pad having opposed first and second pad surfaces, and a third pad surface extending between the first and second pad surfaces, the first pad surface of the die pad defining a peripheral edge and including a first plated pad layer formed thereon which protrudes beyond the peripheral edge of the first pad surface;

a conductive ring having opposed first and second ring surfaces, and a third ring surface extending between the first and second ring surfaces, the first ring surface of the conductive ring defining inner and outer peripheral edges and including a first plated ring layer formed thereon which protrudes beyond the inner and outer peripheral edges of the first ring surface;

a plurality of I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the third surface of each of the I/O pads being inclined such that the first surface is of a first area and the second surface is of a second area which exceeds the first area, the I/O pads being segregated into at least an inner set which extends at least partially about the conductive ring and an outer set which extends at least partially about the inner set, the first surface of each of the I/O pads defining a peripheral edge and including a first plated layer formed thereon which protrudes beyond the peripheral edge of the first surface;

at least one semiconductor die attached and electrically connected to the first plated pad layer of the die pad, the semiconductor die further being electrically connected to the first plated ring layer of the conductive ring and the first plated layer of at least one of the I/O pads; and

a package body at least partially encapsulating the die pad, the conductive ring, the I/O pads, the first plated pad layer, the first plated ring layer, the first plated layer, and the semiconductor die such that at least the second pad surface of the die pad, the second ring surface of the conductive ring and the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.

13. The semiconductor package of claim 12 wherein:

the third pad surface of the die pad is inclined such that the first pad surface is of a first area and the second pad surface is or a second area which exceeds the first area; and

the third ring surface of the conductive ring is inclined such that the first ring surface is of a first area and the second ring surface is of a second area which exceeds the first area.

14. The semiconductor package of claim 13 wherein:

the second pad surface of the die pad includes a second plated pad layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body;

the second ring surface of the conductive ring includes a second plated ring layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body; and

the second surface of each of the I/O pads includes a second plated layer which is farmed thereon and protrudes outwardly beyond the exterior surface of the package body.

15. The semiconductor package of claim 12 wherein the semiconductor die is electrically connected to the first plated pad layer of the die pad, the first plated ring layer of the conductive ring and the first plated layer of each of the I/O pads by conductive wires which are covered by the package body.

16. A semiconductor package, comprising:

a plurality of I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the first surface of each of the I/O pads defining a peripheral edge and including a first plated layer formed thereon which protrudes beyond the peripheral edge of the first surface, the third surface of each of the I/O pads being formed such that the first and second surfaces are of differing areas;

at least one semiconductor die attached and electrically connected to each of the I/O pads; and

a package body at least partially encapsulating the I/O pads and the semiconductor die such that at least the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.

17. The semiconductor package of claim 16 wherein the at least one semiconductor die is electrically connected to the I/O pads by conductive wires which are covered by the package body.

18. The semiconductor package of claim 16 wherein the second surface of each of the I/O pads includes a second plated layer which is formed thereon and protrudes outwardly beyond the exterior surface of the package body.

19. The semiconductor package of claim 16 wherein the semiconductor die is electrically connected to the first plated layer of each of the I/O pads by conductive humps which are covered by the package body.

20. The semiconductor package of claim 16 wherein:

the semiconductor die defines a side surface; and

each of the I/O pads is disposed underneath the semiconductor die inboard of the side surface thereof.

21. A semiconductor package, comprising:

a die pad having opposed first and second pad surfaces, the first pad surface of the die pad defining a peripheral edge and including a first plated pad layer farmed thereon which protrudes beyond the peripheral edge of the first pad surface;

a conductive ring having opposed first and second ring surfaces, the first ring surface of the conductive ring defining inner and outer peripheral edges and including a first plated ring layer formed thereon which protrudes beyond the inner and outer peripheral edges of the first ring surface;

a plurality of I/O pads which each have opposed first and second surfaces, and a third surface which extends between the first and second surfaces, the third surface of each of the I/O pads being inclined such that the first surface is of a first area and the second surface is of a second area which exceeds the first area, the first surface of each of the I/O pads defining a peripheral edge and including a first plated layer formed thereon which protrudes beyond the peripheral edge of the first surface;

at least one semiconductor die attached and electrically connected to the first plated pad layer of the die pad, the semiconductor die further being electrically connected to the first plated ring layer of the conductive ring and the first plated layer of at least one of the I/O pads; and

a package body at least partially encapsulating the die pad, the conductive ring, the I/O pads, the first plated pad layer, the first plated ring layer, the first plated layer, and the semiconductor die such that at least the second pad surface of the die pad, the second ring surface of the conductive ring and the second surfaces of each of the I/O pads are each exposed in a common exterior surface of the package body.