Structure and method for determining a defect in integrated circuit manufacturing process

• US 8,089,297 B2
• Filed: 04/25/2008
• Issued: 01/03/2012
• Est. Priority Date: 04/25/2007
• Status: Active Grant

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: Hermes Microvision, Inc. (ASML Holding NV)
• Inventors: Xiao, Hong, Jau, Jack, Yeh, Chang Chun
• Primary Examiner(s): Toledo, Fernando L
• Application Number:
  US12/110,147
• Publication Number:
  US 20080265251A1
• Time in Patent Office: 1,348 Days
• Field of Search: 324/762.01, 324/762.02, 324/762.03
• US Class Current: 324/762.02
• CPC Class Codes: H01L 22/12 for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions electrical measurement of diffusions H01L22/14
• CPC Class Codes: H01L 22/24 Optical enhancement of defects or not directly visible states, e.g. selective electrolytic deposition, bubbles in liquids, light emission, colour change voltage contrast G01R31/311

Abstract

The present invention discloses a structure and method for determining a defect in integrated circuit manufacturing process, wherein the structure comprises a plurality of normal active areas formed in a plurality of first arrays and a plurality of defective active areas formed in a plurality of second arrays. The first arrays and second arrays are interlaced, and the defect is determined by monitoring a voltage contrast from a charged particle microscope image of the active areas.

Claims

1. A test structure for determining a defect in integrated circuit manufacturing process, comprising:

a plurality of normal active areas formed in a plurality of first arrays on a die; and

a plurality of defective active areas formed in a plurality of second arrays on the die, wherein said first arrays and said second arrays are interlaced,

wherein said defect is determined by monitoring a voltage contrast from a charged particle microscope image of said active areas.

2. The test structure for determining a defect of claim 1, wherein said defect is a void-induced short of said normal active areas or a non-open contact of said normal active areas.

3. The test structure for determining a defect of claim 2, wherein said void-induced short is determined by monitoring the bright voltage contrast image of said active areas.

4. The test structure for determining a defect of claim 2, wherein said non-open contact is determined by monitoring the dark voltage contrast image of said active areas that has large voltage contrast difference.

5. The test structure for determining a defect of claim 1, wherein said active areas are active areas on the die of semiconductor devices.

6. The test structure for determining a defect of claim 5, wherein said normal active areas are active areas of semiconductor devices having heavily n-type doped source and drain, and p-type doped well (N+/P-well).

7. The test structure for determining a defect of claim 5, wherein said detective active areas are active areas of semiconductor devices having heavily p-type doped source and drain with p-type doped well (P+/P-well), heavily n-type doped source and drain with n-type doped well (N+/N-well), heavily p-type doped source and drain with n-type doped well (P+/N-well), p-type doped well (P-well/P-substrate), n-type doped well (N-well/P-substrate), or p-type doped substrate.

8. The test structure for determining a defect of claim 1, wherein every two of said first arrays or second arrays on the die are spaced apart by at least one of said second arrays.

9. The test structure for determining a defect of claim 1, wherein at least two of said first arrays or second arrays on the die are formed side by side.