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Structure and method for determining a defect in integrated circuit manufacturing process

  • US 8,089,297 B2
  • Filed: 04/25/2008
  • Issued: 01/03/2012
  • Est. Priority Date: 04/25/2007
  • Status: Active Grant
First Claim
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1. A test structure for determining a defect in integrated circuit manufacturing process, comprising:

  • a plurality of normal active areas formed in a plurality of first arrays on a die; and

    a plurality of defective active areas formed in a plurality of second arrays on the die, wherein said first arrays and said second arrays are interlaced,wherein said defect is determined by monitoring a voltage contrast from a charged particle microscope image of said active areas.

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