Integrated circuit with through-die via interface for die stacking and cross-track routing

• US 8,089,299 B1
• Filed: 05/07/2009
• Issued: 01/03/2012
• Est. Priority Date: 05/19/2008
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Rahman, Arifur, New, Bernard J.
• Primary Examiner(s): Wilczewski, Mary
• Application Number:
  US12/436,918
• Time in Patent Office: 971 Days
• Field of Search: 326/38, 326/41, 257/686, 257/698, 257/692, 257/E23.174, 257/E21.585, 257/E21.597, 257/208, 438/109, 438/667
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

An integrated circuit die is described that includes an array of tiles arranged in columns. The integrated circuit die includes interface tiles having at least one row of through die vias. The integrated circuit die includes metal layers that include horizontal wiring tracks and metal layers that include vertical wiring tracks. At least some of the metal layers having vertical wiring segments include horizontal wiring segments. Each horizontal wiring segment is coupled to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and is coupled to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias. Each horizontal wiring segment extends between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

Claims

1. A method for coupling wiring of an integrated circuit device comprising:

forming devices on a semiconductor substrate;

forming a first plurality of metal layers that substantially comprise horizontal wiring tracks, the first plurality of metal layers electrically coupled to the devices;

forming a second plurality of metal layers that substantially comprise vertical wiring tracks, the second plurality of metal layers electrically coupled to the devices;

forming rows of through die vias that extend through the first plurality of metal layers and the second plurality of metal layers, the rows of through die vias including at least one row of through die vias that extends within an interface tile, the at least one row of through die vias interrupting a first wiring track on the first plurality of metal layers, the first wiring track including a first wiring segment that extends on one side of the at least one row of through die vias and including a second wiring segment that extends on the opposite side of the at least one row of through die vias; and

forming horizontal wiring segments in the second plurality of metal layers, the horizontal wiring segments including a first horizontal wiring segment that is electrically coupled on one end to the first wiring segment and that is electrically coupled on the other end to the second wiring segment so as to electrically couple the first wiring segment to the second wiring segment.

2. The method of claim 1 wherein the first horizontal wiring segment extends between the plurality of rows of through die vias and a row of through die vias in an adjoining interface tile.

3. The method of claim 2 further comprising:

forming a plurality of vertical wiring segments including a first vertical wiring segment and a second vertical wiring segment, the first vertical wiring segment electrically coupled on one end to the first wiring segment and electrically coupled on the other end to the first horizontal wiring segment, the second vertical wiring segment electrically coupled on one end to the second wiring segment and electrically coupled on the other end to the first horizontal wiring segment.

4. The method of claim 3 further comprising forming a first plurality of vias that extend between individual of the plurality of vertical wiring segments and individual of the plurality of horizontal wiring segments.

5. The method of claim 4 further comprising forming a second plurality of vias that include a third via and a fourth via, the third via extending between the first wiring segment and the first vertical wiring segment and the fourth via extending between the second wiring segment and the second vertical wiring segment.

6. The method of claim 3 further comprising:

forming an additional metal layer that connects to the at least one row of through die vias, the first plurality of metal layers and the second plurality of metal layers extending between the additional metal layer and the substrate of the integrated circuit die; and

forming contacts on the backside of the integrated circuit die that are electrically coupled to the at least one row of through die vias.

7. The method of claim 1 further comprising:

generating through die via layouts and corresponding wiring layouts, with each subsequent through die via layout having a reduced number of rows of through die vias, until a wiring layout is generated that routes all required connections;

increasing wiring width and spacing of each wiring layout that routes all required connections and that does not meet timing criteria; and

continuing the generating through die via layouts and corresponding wiring layouts, and the increasing wiring width and spacing until a wiring layout is obtained that routes all required connections and that meets the timing criteria.

8. An integrated circuit die having an array of tiles arranged in columns, comprising:

an interface tile that includes at least one row of through die vias;

a first plurality of metal layers that include horizontal wiring tracks; and

a second plurality of metal layers that include vertical wiring tracks, at least some of the second plurality of metal layers including horizontal wiring segments, each horizontal wiring segment coupling to a first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias and coupling to a second wiring segment of the horizontal wiring track that is interrupted by the at least one row of through die vias, each horizontal wiring segment extending between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile.

9. The integrated circuit die of claim 8, further comprising an additional metal layer that electrically connects to the at least one row of through die vias, wherein the at least one row of through die vias, the first plurality of metal layers and the second plurality of metal layers extend between the additional metal layer and the backside of the integrated circuit die, wherein the at least one row of through die vias extend through each of the metal layers in the first plurality of metal layers and the second plurality of metal layers.

10. The integrated circuit die of claim 9 further comprising a plurality of vertical wiring segments, the plurality of vertical wiring segments including a first vertical wiring segment and a second vertical wiring segment, the first vertical wiring segment electrically coupled on one end to one of the horizontal wiring segments and electrically coupled on the other end to the first wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias, the second vertical wiring segment electrically coupled on one end to one of the horizontal wiring segments and electrically coupled on the other end to the second wiring segment of a horizontal wiring track that is interrupted by the at least one row of through die vias.

11. The integrated circuit die of claim 8, wherein the first wiring segment of the horizontal wiring track that is interrupted by a through die via, the second wiring segment of the horizontal wiring track that is interrupted by a through die via and the horizontal wiring segments form a part of a routing fabric of a field programmable gate array integrated circuit device, and wherein the interface tile comprises contacts on a backside of the integrated circuit die, the at least one row of through die vias electrically coupled to the contacts.

12. The integrated circuit die of claim 11 wherein the interface tile comprises:

at least one programmable interconnect element coupled to the routing fabric;

a configurable logic element;

a first interface circuit coupled to a first plurality of the through die vias;

a second interface circuit coupled to a second plurality of the through die vias; and

selection logic for selectively coupling first signals from the at least one programmable interconnect element to either the configurable logic element or the first interface circuit, and second signals to the at least one programmable interconnect element from either the configurable logic element or the second interface circuit.

13. The integrated circuit die of claim 9, wherein, with the exception of the horizontal wiring segments, all wiring on the second plurality of metal layers extends vertically.

14. The integrated circuit die of claim 9, wherein, with the exception of the horizontal wiring segments, none of the wiring on the second plurality of metal layers extends horizontally.

15. The integrated circuit die of claim 9, wherein at least some of the vertical wiring segments extend within the first plurality of metal layers, and further wherein, with the exception of the vertical wiring segments, none of the wiring on the first plurality of metal layers extends vertically.

16. The integrated circuit die of claim 9, wherein at least some of the vertical wiring segments extend within the first plurality of metal layers, and further wherein, with the exception of the vertical wiring segments, all of the wiring on the first plurality of metal layers extends horizontally.

17. A device having an array of tiles arranged in columns, comprising:

an interface tile on a first integrated circuit die, the interface tile including at least one row of through die vias that are coupled to contacts attached to a backside of the first integrated circuit die and including a logic element coupled to a routing fabric of the first integrated circuit die;

a first plurality of metal layers on the first integrated circuit die, each of the first plurality of metal layers including a first plurality of wiring tracks that are oriented in a first direction;

a second plurality of metal layers on the first integrated circuit die, each of the second plurality of metal layers including a second plurality of wiring tracks that are oriented approximately orthogonally to the first direction, at least some of the second plurality of metal layers including first wiring segments, each first wiring segment coupling to a first wiring segment of a wiring track in the first plurality of wiring tracks that is interrupted by the at least one row of through die vias and coupling to a second wiring segment of the wiring track in the first plurality of wiring tracks that is interrupted by the at least one row of through die vias, each first wiring segment extending between the at least one row of through die vias and at least one row of through die vias in an adjoining interface tile; and

second wiring segments on the first integrated circuit die, a first of the second wiring segments electrically coupled on one end to one of the first wiring segments and electrically coupled on the other end to the first wiring segment of a wiring track in the first plurality of wiring tracks that is interrupted by the at least one row of through die vias, a second of the second wiring segments electrically coupled on one end to one of the first wiring segments and electrically coupled on the other end to the second wiring segment of a wiring track in the first plurality of wiring tracks that is interrupted by the at least one row of through die vias.

18. The device of claim 17, further comprising an additional metal layer on the first integrated circuit die, the additional metal layer electrically connected to the at least one row of through die vias, wherein the at least one row of through die vias, the first plurality of metal layers and the second plurality of metal layers extend between the additional metal layer and the substrate of the first integrated circuit die, wherein the at least one row of through die vias extend through each of the metal layers in the first plurality of metal layers and the second plurality of metal layers.

19. The device of claim 18, further comprising a second integrated circuit die that is attached to the backside of the first integrated circuit die, the second integrated circuit die electrically coupled to the contacts.

20. The device of claim 19, wherein, with the exception of the first wiring segments, all wiring on the second plurality of metal layers extends approximately orthogonally to the first direction.