Users registers implemented with routing circuits in a configurable IC

• US 8,089,300 B2
• Filed: 02/08/2010
• Issued: 01/03/2012
• Est. Priority Date: 12/01/2005
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason
• Primary Examiner(s): CRAWFORD, JASON
• Application Number:
  US12/702,290
• Publication Number:
  US 20100213977A1
• Time in Patent Office: 694 Days
• Field of Search: 326 37- 4147, 327/218
• US Class Current: 326/40
• CPC Class Codes: H03K 19/17744 for input/output signals
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

Claims

1. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits, each for configurably performing a set of functions; and

a plurality of configurable routing circuits for configurably routing signals to and from said plurality of configurable logic circuits, wherein a first configurable routing circuit and a second configurable routing circuit are communicatively coupled to form a single data register that receives and holds a signal at the first configurable routing circuit for a period of time before storing the signal at the second configurable routing circuit.

2. The IC of claim 1, wherein said period of time comprises a plurality of clock cycles.

3. The IC of claim 1, wherein each of the first and second configurable routing circuits comprises a multiplexer and a latch.

4. The IC of claim 1, wherein said first configurable routing circuit and said second configurable routing circuit are communicatively coupled through a set of configurable circuits.

5. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits, each for configurably performing a set of functions; and

a plurality of configurable routing circuits for configurably routing signals to and from said plurality of configurable logic circuits, wherein a first configurable routing circuit and a second configurable routing circuit are communicatively coupled through a set of configurable circuits to form a single data register, wherein the set of configurable circuits is for holding a signal received by said first configurable routing circuit for one or more clock cycles before sending the signal to be stored at said second configurable routing circuit.

6. An integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits, each for configurably performing a set of functions; and

a routing fabric comprising;

a plurality of configurable routing circuits for configurably routing signals to and from said plurality of configurable logic circuits; and

a plurality of configurable latches including first and second configurable latches, wherein the first configurable latch and the second configurable latch are communicatively coupled in a master-slave arrangement to form a single data register.

7. The IC of claim 6, wherein said single data register receives and holds a signal at the first configurable latch for a period of time before storing the signal at the second configurable latch.

8. The IC of claim 7, wherein said period of time comprises a plurality of clock cycles.

9. The IC of claim 6, wherein said first configurable latch and said second configurable latch are communicatively coupled through a set of configurable circuits.

10. The IC of claim 9, wherein the set of configurable circuits are configured to pass-through a signal received by said first configurable latch to be stored at said second configurable latch.

11. The IC of claim 10, wherein the set of configurable circuits comprises one or more configurable interconnect elements.

12. The IC of claim 11, wherein the set of configurable circuits further comprises one or more configurable routing circuits.

13. An electronic device comprising:

a memory device that stores configuration data sets; and

an integrated circuit (“

IC”

) comprising;

a plurality of configurable logic circuits, each for configurably performing a set of functions according to a plurality of the configuration data sets; and

a routing fabric comprising;

a plurality of configurable routing circuits for configurably routing signals to and from said plurality of configurable logic circuits; and

a plurality of configurable latches including first and second configurable latches, wherein the first configurable latch and the second configurable latch are communicatively coupled in a master-slave arrangement to form a single data register.

14. The electronic device of claim 13, wherein said single data register receives and holds a signal at the first configurable latch for a period of time before storing the signal at the second configurable latch.

15. The electronic device of claim 14, wherein said period of time comprises a plurality of clock cycles.

16. The electronic device of claim 13, wherein said first configurable latch and said second configurable latch are communicatively coupled through a set of configurable circuits.

17. The electronic device of claim 16, wherein the set of configurable circuits are configured to pass a signal received by said first configurable latch to be stored at said second configurable latch.

18. The electronic device of claim 17, wherein the set of configurable circuits comprises one or more configurable interconnect elements.

19. The electronic device of claim 18, wherein the set of configurable circuits further comprises one or more configurable routing circuits.