Programmable digital-to-analog converter

• US 8,089,384 B1
• Filed: 04/05/2010
• Issued: 01/03/2012
• Est. Priority Date: 05/10/2009
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Williams, Timothy J., Shutt, James H., Snyder, Warren, Seguine, Dennis
• Primary Examiner(s): Williams, Howard
• Application Number:
  US12/754,431
• Time in Patent Office: 638 Days
• Field of Search: 341/133, 341/135, 341/136, 341/144
• US Class Current: 341/144
• CPC Class Codes: H03M 1/005 among different converters types
• CPC Class Codes: H03M 1/742 using current sources as quantisation value generators

Abstract

A multi-mode digital-to-analog converter (DAC) configured to operate in a plurality of modes.

Claims

1. A circuit, comprising

a digital-to-analog converter (DAC) configured to receive a digital code input, wherein the DAC comprises:

a first output terminal configured to provide a current output based on the digital code input;

a second output terminal configured to provide a voltage output based on the digital code input; and

a first selection circuit coupled to receive an input voltage reference and an input current reference, the first selection circuit configured to utilize the input voltage reference to provide either or both the current output or the voltage output when the input voltage reference is selected and to utilize the input current reference to provide either or both the current output or the voltage output when the input current reference is selected.

2. The circuit of claim 1, wherein the DAC further comprises a mode-select terminal configured to select one of a plurality of modes for the DAC, and wherein the DAC is configured to provide the current output when a current mode is selected and the voltage output when a voltage mode is selected.

3. The circuit of claim 2, wherein at least one of the plurality of modes comprises a voltage-current mode, and wherein the DAC is configured to provide the current output and the voltage output concurrently when the voltage-current mode is selected.

4. The circuit of claim 2, wherein the plurality of modes comprise a current source mode and a current sink mode, and wherein the DAC is configured to provide a current source for the current output when the current source mode is selected and provide a current sink for the current output when the current source mode is selected.

5. The circuit of claim 2, wherein the DAC further comprises:

a DAC array configured to receive the digital code input and provide an analog current output;

a current output circuit coupled to the DAC array, wherein the current output circuit is configured to receive the analog current output from the DAC array and a current range input, and to provide the current output on the first output terminal according to the analog current output and the current range input; and

a voltage output circuit coupled to the DAC array, wherein the voltage output circuit is configured to receive the analog current output from the DAC array and a voltage range input, and to provide the voltage output on the second output terminal according to the analog current output and the voltage range input.

6. The circuit of claim 5, wherein the current output circuit comprises:

a decoder configured to receive a selection input configured to select whether the current output circuit provides a current source or a current sink for the current output on the first output terminal, and to receive the current range input configured to scale the current output on the first output terminal, wherein the decoder is configured to provide a plurality of switch controls; and

a plurality of current minors configured to provide the current output on the first output terminal based on the plurality of switch controls.

7. The circuit of claim 6, wherein the plurality of current mirrors comprises:

a first N-type current minor configured to receive the analog current output from the DAC array, and provide a first output reference;

a plurality of N-type scaling current minors coupled to the first N-type current mirror, wherein the plurality of N-type scaling current mirrors are each configured to receive the first output reference and produce a scaled current output according to a corresponding scaling value of the respective N-type scaling current mirror, wherein the plurality of N-type scaling current mirrors provide the current sink for the current output on the first output terminal;

a first P-type current minor coupled to the first N-type current mirror, wherein the first P-type current minor is configured to provide a second output reference;

a plurality of P-type scaling current minors coupled to the first P-type current mirror, wherein the plurality of P-type scaling current mirrors are each configured to receive the second output reference and produce a scaled current output according to a corresponding scaling value of the respective P-type scaling current mirror, wherein the plurality of P-type scaling current mirrors provide the current source for the current output on the first output terminal; and

a plurality of switches, each of which is coupled to outputs of the plurality of N-type scaling current mirrors and the plurality of P-type scaling current minors, and wherein each of the plurality of switches is configured to be controlled by one of the plurality of switch controls provided by the decoder.

8. The circuit of claim 5, wherein the voltage output circuit is configured to convert the analog current output from the DAC array into the voltage output, and wherein the voltage output circuit comprises a selectable resistance to scale the voltage output according to the voltage range input.

9. The circuit of claim 5, wherein the DAC further comprises a trimming circuit configured to receive a trimming input for each of the plurality of modes, and wherein the trimming circuit is configured to adjust a gain of the DAC array to adjust the analog current output of the DAC array.

10. The circuit of claim 5, wherein the first selection circuit comprises a first switch and a second switch, wherein the first switch is configured to receive the input current reference and is configured to provide the input current reference to the DAC array as an analog current input when the input current reference is selected, and wherein the second switch is configured to receive a second current reference and is configured to provide the second current reference to the DAC array as the analog current input when the input voltage reference is selected, wherein the second current reference is representative of the input voltage reference.

11. The circuit of claim 10, further comprising a voltage-to-current converter configured to convert the input voltage reference to the second current reference.

12. A circuit, comprising

a multi-mode digital-to-analog converter (DAC) to operate in a plurality of modes including at least a current mode and a voltage mode, wherein the multi-mode DAC is configured to receive a digital code input, to provide an analog current output, corresponding to the digital code input, when in the current mode, to provide a voltage output, corresponding to the digital code input, when in the voltage mode, wherein the multi-mode DAC is configured to receive an input voltage reference and an input current reference, and wherein the multi-mode DAC is configured to utilize the input voltage reference to provide either or both the current output or the voltage output when the input voltage reference is selected and to utilize the input current reference to provide either or both the current output or the voltage output when the input current reference is selected.

13. The circuit of claim 12, wherein the multi-mode DAC comprises a programmable output range for each of the plurality of modes, including a multi-range current output when the multi-mode DAC is in the current mode and a multi-range voltage output when the multi-mode DAC is in the voltage mode.

14. The circuit of claim 12, wherein the multi-mode DAC comprises a programmable trimming circuit configured to individually adjust the analog current output and the voltage output for each of the plurality of modes.

15. The circuit of claim 12, wherein the multi-mode DAC comprises a programmable current output circuit to select a current sink for the analog current output or a current source for the analog current output.

16. The circuit of claim 12, further comprising a DAC, wherein an output of the DAC is combined with at least one of the analog current output and the voltage output of the multi-mode DAC.

17. A method, comprising:

receiving a digital code input at a multi-mode digital-to-analog converter (DAC), the multi-mode DAC to operate in a plurality of modes including at least a current mode and a voltage mode;

providing a current output, corresponding to the digital code input, when in the current mode;

providing a voltage output, corresponding to the digital code input, when in the voltage mode; and

receiving at the multi-mode DAC an input voltage reference and an input current reference;

selecting between the input voltage reference and the input current reference for either or both said providing the current output and said providing the voltage output.

18. The method of claim 17, further comprising providing the current output and the voltage output concurrently when one of the plurality of modes is selected.

19. The method of claim 17, wherein providing the current output comprises selecting one of a current sink mode and a current source mode of the plurality of modes, and wherein said providing the current output comprises:

providing the current output as a current sink when the current sink mode is selected; and

providing the current output as a current source when the current source mode is selected.

20. The method of claim 17, further comprising:

receiving a current range input at the multi-mode DAC while the multi-mode DAC operates in the current mode;

scaling the current output based on the current range input;

receiving a voltage range input at the multi-mode DAC while the multi-mode DAC operates in the voltage mode; and

scaling the voltage output based on the voltage range input.

21. The method of claim 17, further comprising:

receiving a trimming input at the multi-mode DAC;

adjusting the current output according to the trimming input when the multi-mode DAC operates in the current mode; and

adjusting the voltage output according to the trimming input when the multi-mode DAC operates in the voltage mode.

22. The method of claim 17, further comprising combining an output of a DAC with at least one of the current output and the voltage output of the multi-mode DAC.