Method and system of providing a high speed Tomlinson-Harashima Precoder

• US 8,090,013 B2
• Filed: 03/06/2008
• Issued: 01/03/2012
• Est. Priority Date: 03/15/2007
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Farhoodfar, Arash, Kota, Kishore, Kwentus, Alan, Hwang, David
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): Hassan, Sarah
• Application Number:
  US12/043,751
• Publication Number:
  US 20080225937A1
• Time in Patent Office: 1,398 Days
• Field of Search: 375/232, 375/285, 348/607
• US Class Current: 375/232
• CPC Class Codes: H04L 25/497 by correlative coding, e.g. partial response coding or echo modulation coding transmitters and receivers for partial response systems transversal equalizers at the transmitter end H04L25/03343
• CPC Class Codes: H04L 25/4975 Correlative coding using Tomlinson precoding, Harashima precoding, Trellis precoding or GPRS

Abstract

Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Claims

1. A method of processing a discrete time sampled sequence by a Tomlinson-Harashima Precoder (THP) comprising:

receiving a first discrete time sampled sequence by an L-tap Tomlinson-Harashima Precoder (THP);

receiving a clock signal by said L-tap Tomlinson-Harashima Precoder (THP), said clock signal having a clock rate equal to one half the symbol rate of said discrete time sampled sequence;

using L state variables to express one or more outputs of said L-tap Tomlinson-Harashima Precoder (THP);

processing said first discrete time sampled sequence using L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal; and

outputting a second discrete time sampled sequence by said L-tap Tomlinson-Harashima Precoder.

2. The method of claim 1 wherein said L-tap Tomlinson-Harashima Precoder (THP) comprises a transpose form configuration.

3. The method of claim 1 wherein said L coefficients comprise coefficients of a least mean square adaptive digital filter.

4. The method of claim 1 wherein L equals 16.

5. The method of claim 1 wherein said processing comprises performing a lookup of a linear combination of two of said L state variables, said lookup performed using an addressable memory.

6. The method of claim 5 wherein said lookup outputs a value:

−

1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is greater than or equal to an integer value, M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

+1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is less than −

M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

or

0, if otherwise.

7. The method of claim 1 wherein said processing comprises performing a number of add and multiply operations using said coefficients and said state variables.

8. The method of claim 7 wherein said add operations are performed using one or more carry-save adders.

9. The method of claim 7 wherein said add operations are performed using one or more carry-propagate adders.

10. The method of claim 1 wherein said processing comprises performing a number of modulo 2M operations using said coefficients and said state variables, wherein M corresponds to an integer value.

11. An L-tap Tomlinson-Harashima Precoder (THP) comprising:

at least one circuitry for receiving a first discrete time sampled sequence;

said at least one circuitry for receiving a clock signal, wherein said clock rate is equal to one half the rate of the symbol rate of said first discrete time sampled sequence;

said at least one circuitry for receiving L coefficients, said at least one circuitry for using L state variables to express one or more outputs of said L-tap Tomlinson-Harashima Precoder (THP);

said at least one circuitry for processing said first discrete time sampled sequence using said L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal; and

said at least one circuitry for outputting a second discrete time sampled sequence.

12. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein said L-tap Tomlinson-Harashima Precoder (THP) comprises a transpose form configuration.

13. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein said L coefficients comprise coefficients of a least mean square adaptive digital filter.

14. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein L equals 16.

15. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein said processing comprises performing a lookup of a linear combination of two of said L state variables, said lookup performed using an addressable memory.

16. The L-tap Tomlinson-Harashima Precoder (THP) of claim 15 wherein said lookup outputs a value:

−

1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is greater than or equal to an integer value, M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

+1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is less than −

M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

or

0, if otherwise.

17. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein said processing comprises performing a number of add and multiply operations using said coefficients and said state variables.

18. The L-tap Tomlinson-Harashima Precoder (THP) of claim 17 wherein said add operations are performed using one or more carry-save adders.

19. The L-tap Tomlinson-Harashima Precoder (THP) of claim 17 wherein said add operations are performed using one or more carry-propagate adders.

20. The L-tap Tomlinson-Harashima Precoder (THP) of claim 11 wherein said processing comprises performing a number of modulo 2M operations using said coefficients and said state variables, wherein M corresponds to an integer value.

21. An L-tap Tomlinson-Harashima Precoder (THP) comprising:

a single integrated circuit chip, said integrated circuit chip comprising;

at least one circuitry for receiving a first discrete time sampled sequence,

said at least one circuitry for receiving a clock signal, said clock rate equal to one half the rate of the symbol rate of said first discrete time sampled sequence,

said at least one circuitry for using L state variables to express one or more outputs of said Tomlinson-Harashima Precoder (THP),

said at least one circuitry for processing said first discrete time sampled sequence using L coefficients and said L state variables by clocking said first discrete time sampled sequence using said clock signal, and

said at least one circuitry for outputting a second discrete time sampled sequence.

22. The L-tap Tomlinson-Harashima Precoder (THP) of claim 21 wherein said L-tap Tomlinson-Harashima Precoder (THP) comprises a transpose form configuration.

23. The L-tap Tomlinson-Harashima Precoder (THP) of claim 21 wherein said L coefficients comprise coefficients of a least mean square adaptive digital filter.

24. The L-tap Tomlinson-Harashima Precoder (THP) of claim 21 wherein L equals 16.

25. The L-tap Tomlinson-Harashima Precoder (THP) of claim 21 wherein said processing comprises performing a lookup of a linear combination of two of said L state variables, said lookup performed using an addressable memory.

26. The L-tap Tomlinson-Harashima Precoder (THP) of claim 25 wherein said lookup outputs a value:

−

1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is greater than or equal to an integer value, M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

+1, if the sum of the output of the second stage of said L-tap Tomlinson-Harashima Precoder (THP) and a product is less than −

M, wherein said product is equal the output of the first stage of said L-tap THP multiplied by the c₁ coefficient of said L coefficients;

or

0, if otherwise.

27. The L-tap Tomlinson-Harashima Precoder (THP) of claim 21 wherein said processing comprises performing a number of add and multiply operations using said coefficients and said state variables.

28. The L-tap Tomlinson-Harashima Precoder (THP) of claim 27 wherein said add operations are performed using one or more carry-save adders.

29. The L-tap Tomlinson-Harashima Precoder (THP) of claim 27 wherein said add operations are performed using one or more carry-propagate adders.

30. The L-tap Tomlinson-Harashima Precoder (THP) of claim 24 wherein said processing comprises performing a number of modulo 2M operations using said coefficients and said state variables, wherein M corresponds to an integer value.