Multi-viterbi receive channel decoder

• US 8,090,059 B1
• Filed: 05/01/2007
• Issued: 01/03/2012
• Est. Priority Date: 05/01/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Song, Hongwei, Wu, Zining, Yang, Shaohua
• Primary Examiner(s): Tran, Khanh C
• Assistant Examiner(s): Ghulamali, Qutbuddin
• Application Number:
  US11/799,488
• Time in Patent Office: 1,708 Days
• Field of Search: 375/341, 375/232, 375/233, 375/350
• US Class Current: 375/341
• CPC Class Codes: G11B 20/1803 by redundancy in data representation
• CPC Class Codes: H03M 13/3746 with iterative decoding
• CPC Class Codes: H03M 13/41 using the Viterbi algorithm or Viterbi processors
• CPC Class Codes: H03M 13/6343 Error control coding in combination with techniques for partial response channels, e.g. recording
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Abstract

A detector includes Viterbi detectors. A first Viterbi detector generates a preliminary decision signal. A second Viterbi detector generates a final decision signal based on an input data signal and the preliminary decision signal. The second Viterbi detector is arranged in series with the first Viterbi detector.

Claims

1. A detection circuit comprising:

an impulse response filter configured to generate an equalized signal based on an input data signal;

a first Viterbi detector configured to generate at least one preliminary decision signal including preliminary non-return-to-zero data estimates based on the equalized signal;

a plurality of filters configured to (i) receive the at least one preliminary decision signal and (ii) generate a filtered signal based on the at least one preliminary decision signal; and

a second Viterbi detector (i) arranged in series with the first Viterbi detector and (ii) configured to generate a final decision signal including final non-return-to-zero estimates based on a sum of (i) a delayed version of the equalized signal and (ii) the filtered signal.

2. The detection circuit of claim 1, wherein:

the first Viterbi detector is configured to generate a plurality of preliminary decision signals; and

the plurality of filters are configured to (i) receive the plurality of preliminary decision signals and (ii) generate the final decision signal based on the plurality of preliminary decision signals.

3. The detection circuit of claim 1, wherein:

the first Viterbi detector is configured to generate a first preliminary decision signal and a second preliminary decision signal, wherein the first preliminary decision signal has a longer associated depth than the second preliminary decision signal; and

the plurality of filters are configured to (i) receive first preliminary decision signal and the second preliminary decision signal and (ii) generate the final decision signal based on the first preliminary decision signal and the second preliminary decision signal.

4. The detection circuit of claim 1, wherein:

the first Viterbi detector has a first depth; and

the second Viterbi detector has a second depth.

5. The detection circuit of claim 4, wherein the first depth is longer than the second depth.

6. The detection circuit of claim 1, wherein:

the plurality of filters comprise a filter bank;

the filter bank is configured to generate the filtered signal based on the at least one preliminary decision signal; and

the second Viterbi detector is configured to generate the final decision signal based on the filtered signal.

7. The detection circuit of claim 6, wherein:

the filter bank comprises filters configured to generate a plurality of filtered signals; and

the second Viterbi detector is configured to generate the final decision signal based on the plurality of filtered signals.

8. The detection circuit of claim 7, wherein the plurality of filters are arranged in parallel relative to each other.

9. The detection circuit of claim 1, further comprising:

a first delay device configured to generate a first delay signal;

a reconstruction filter configured to generate a first reconstruction data signal based on the at least one preliminary decision signal; and

a first summer configured to generate an error signal based on (i) the first delay signal and (ii) the first reconstruction data signal.

10. The detection circuit of claim 9, wherein:

the reconstruction filter is configured to generate a second reconstruction data signal based on the at least one preliminary decision signal; and

the second Viterbi detector is configured to generate the final decision signal based on the second reconstruction data signal.

11. The detection circuit of claim 1, wherein:

the plurality of filters comprise a reconstruction filter configured to generate a reconstruction data signal based on the at least one preliminary decision signal; and

the second Viterbi detector in configured to generate a final decision signal based on the reconstruction data signal.

12. The detection circuit of claim 1, further comprising a delay circuit configured to generate a pre-filtered signal based on a reconstruction data signal, wherein the plurality of filters comprises:

a reconstruction filter configured to generate the reconstruction data signal based on the preliminary decision signal; and

a filter bank configured to generate the filtered signal based on the pre-filtered signal.

13. A detection circuit comprising:

a first Viterbi detector configured to output at least one preliminary decision signal; and

a second Viterbi detector (i) arranged in series with the first Viterbi detector and (ii) configured to generate a final decision signal, wherein the second Viterbi detector is configured to generate the final decision signal based on (i) an input data signal and (ii) the at least one preliminary decision signal;

a first delay device configured to generate a first delay signal;

a reconstruction filter configured to generate a first reconstruction data signal based on the at least one preliminary decision signal;

a first summer configured to generate an error signal based on (i) the first delay signal and (ii) the at least one preliminary decision signal;

a second delay device configured to generate a second delay signal based on the first delay signal; and

a second summer configured to generate a pre-filtered signal based on (i) the second delay signal and (ii) the first reconstruction data signal,

wherein the second Viterbi detector is configured to generate the final decision signal based on (i) the second delay signal and (ii) the pre-filtered signal.

14. The detection circuit of claim 13, further comprising:

a third delay device configured to generate a third delay signal based on the second delay signal;

a filter bank configured to generate at least one filtered signal based on the pre-filtered signal; and

a third summer configured to generate a pre-finalized decision signal based on (i) the third delay signal and (ii) the at least one filtered signal,

wherein the second Viterbi detector is configured to generate the final decision signal based on the pre-finalized decision signal.

15. A detection circuit comprising:

a plurality of filters configured to generate (i) an equalized signal based on an input signal and (ii) a filtered signal; and

a detector module comprising a plurality of Viterbi detectors (i) arranged in series and (ii), configured to generate a final decision signal including final non-return-to-zero estimates,

wherein the detector module is configured to generate the final decision signal based on a pre-finalized decision signal fed forward to one of the plurality of Viterbi detectors, wherein the pre-finalized decision signal is equal to a sum of (i) a delayed version of the equalized signal and (ii) the filtered signal.

16. The detection circuit of claim 15, further comprising at least one feedback loop configured to receive an error signal from the detector module.

17. The detection circuit of claim 16, wherein the detector module is configured to generate the final decision signal based on the error signal.

18. The detection circuit of claim 16, wherein the at least one feedback loop comprises at least one of a timing loop, a gain loop, a filter loop, or a baseline loop.

19. The detection circuit of claim 16, wherein the at least one feedback loop comprises a timing loop, a gain loop, a filter loop, and a baseline loop.

20. The detection circuit of claim 16, wherein:

the at least one feedback loop comprises a timing loop;

the timing loop is configured to generate a timing signal based on the error signal; and

the plurality of Viterbi detectors are configured to generate the finalized decision signal based on the timing signal.

21. The detection circuit of claim 16, wherein:

the at least one feedback loop comprises a gain loop;

the gain loop is configured to generate a gain signal based on the error signal; and

the plurality of Viterbi detectors configured to generate the finalized decision signal based on the gain signal.

22. The detection circuit of claim 16, wherein:

the at least one feedback loop comprises a filter loop;

the filter loop is configured to generate a weight signal based on the error signal; and

the plurality of Viterbi detectors is configured to generate the finalized decision signal based on the weight signal.

23. The detection circuit of claim 16, wherein:

the at least one feedback loop comprises a baseline loop;

the baseline loop is configured to generate a correction signal based on the error signal; and

the plurality of Viterbi detectors is configured to generate the finalized decision signal based on the correction signal.

24. The detection circuit of claim 15, wherein the plurality of Viterbi detectors comprise:

a first Viterbi detector configured to generate at least one preliminary decision signal preliminary non-return-to-zero data estimates; and

a second Viterbi detector configured to generate the final decision signal based on the at least one preliminary decision signal, wherein the one of the plurality of Viterbi detectors is the second Viterbi detector.

25. The detection circuit of claim 24, further comprising:

a reconstruction filter configured to generate an error signal based on the at least one preliminary decision signal;

at least one feedback loop configured to generate a compensation signal based on the error signal; and

a response filter configured to generate the equalized signal based on (i) an input signal and (ii) the compensation signal.

26. The detection circuit of claim 15, wherein the plurality of Viterbi detectors comprise:

a first Viterbi detector configured to (i) receive the equalized signal and (ii) generate a preliminary decision signal including preliminary non-return-to-zero data estimates based on the equalized signal; and

a second Viterbi detector configured to generate final decision signal based on a sum of (i) a delayed version of the equalized signal and (ii) the filtered signal.

27. The detection circuit of claim 26, further comprising:

a reconstruction filter configured to generate a reconstruction data signal based on the preliminary decision signal;

a summing device configured to generate a prefilter signal based on the reconstruction data signal and a delayed version of the equalized signal; and

a filter bank configured to generate the filtered signal based on the prefiltered signal.

28. A method of operating a read channel decoder, the method comprising:

generating an equalized signal based on an input data signal;

generating at least one preliminary decision signal including preliminary non-return-to-zero data estimates via a first Viterbi detector and based on the equalized signal;

via a plurality of filters, (i) receiving the at least one preliminary decision signal and (ii) generating a filtered signal based on the at least one preliminary decision signal; and

via a second Viterbi detector, generating a final decision signal including final non-return-to-zero data estimates based on a sum of (i) a delayed version of the equalized signal and (ii) a filtered signal.

29. The method of claim 28, further comprising:

generating a plurality of preliminary decision signals; and

receiving the plurality of preliminary decision signals via the plurality of filters,

wherein the final decision signal is generated based on the plurality of preliminary decision signals.

30. The method of claim 28, further comprising:

generating a first preliminary decision signal and a second preliminary decision signal, wherein the first preliminary decision signal has a longer associated depth than the second preliminary decision signal; and

via the plurality of filters

receiving the first preliminary decision signal and the second preliminary decision signal, and

generating the final decision signal based on the first preliminary decision signal and the second preliminary decision signal.

31. The method of claim 28, further comprising generating the filtered signal based on the at least one preliminary decision signal, wherein the final decision signal is generated based on the filtered signal.

32. The method of claim 31, further comprising generating a plurality of filtered signals, wherein the final decision signal is generated based on the plurality of filtered signals.

33. The method of claim 28, further comprising:

generating a first delay signal;

generating a first reconstruction data signal based on the at least one preliminary decision signal; and

generating an error signal based on (i) the first delay signal and (ii) the first reconstruction data signal.

34. The method of claim 33, further comprising generating a second reconstruction data signal based on the at least one preliminary decision signal, wherein the final decision signal is generated based on the second reconstruction data signal.

35. The method of claim 33, further comprising:

generating a second delay signal based on the first delay signal;

generating a pre-filtered signal based on (i) the second delay signal and (ii) the first reconstruction data signal; and

generating the final decision signal based on (i) the second delay signal and (ii) the pre-filtered signal.

36. The method of claim 35, further comprising:

generating a third delay signal based on the second delay signal;

generating at least one filtered signal based on the pre-filtered signal;

generating a pre-finalized decision signal based on (i) the third delay signal and (ii) the at least one filtered signal; and

generating the final decision signal based on the pre-finalized decision signal.

37. A method of operating a read channel decoder, the method comprising:

generating an equalized signal based on an input signal;

generating a filtered signal;

generating a pre-finalized decision signal by sum (i) a delayed version of the equalized signal and (ii) the filtered signal; and

generating a final decision signal including final non-return-to-zero estimates based on the pre-finalized decision signal fed forward to one of a plurality of Viterbi detectors, wherein the plurality of Viterbi detectors are serially arranged relative to each other.

38. The method of claim 37, further comprising:

receiving an error signal; and

generating the final decision signal based on the error signal.

39. The method of claim 38, further comprising generating a timing signal based on the error signal, wherein the finalized decision signal is generated based on the timing signal.

40. The method of claim 38, further comprising generating a gain signal based on the error signal, wherein the finalized decision signal is generated based on the gain signal.

41. The method of claim 38, further comprising generating a weight signal based on the error signal, wherein the finalized decision signal is generated based on the weight signal.

42. The method of claim 38, further comprising generating a correction signal based on the error signal, wherein the finalized decision signal is generated based on the correction signal.

43. The method of claim 37, further comprising:

generating a preliminary decision signal; and

generating the final decision signal based on the preliminary decision signal.

44. The method of claim 43, further comprising:

generating an error signal based on the preliminary decision signal;

generating a compensation signal based on the error signal;

generating an equalized signal based on an input signal and the compensation signal; and

generating the final decision signal based on the equalized signal.