System and method for expanding PCIe compliant signals over a fiber optic medium with no latency

• US 8,090,263 B2
• Filed: 08/24/2007
• Issued: 01/03/2012
• Est. Priority Date: 08/24/2007
• Status: Active Grant

• Current Assignee: RJ Intellectual Property LLC
• Original Assignee: Mission Technology Group, Inc. (One Stop Systems Incorporated)
• Inventors: Mussatt, Kip, Stefanescu, Marius
• Primary Examiner(s): PASCAL, LESLIE C
• Application Number:
  US11/895,376
• Publication Number:
  US 20090052903A1
• Time in Patent Office: 1,593 Days
• Field of Search: 398115-118, 398135-139
• US Class Current: 398/116
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A system for expanding PCI Express (PCIe) compliant signals over a fiber optic medium with no latency. A standardized fiber optic transceiver is adapted to provide an optimal PCIe expansion over a fiber optic medium. Signal buffers are utilized to translate and fine-tune standardized PCIe traffic to a level of low voltage differential signaling (LVDS) that is comprehensible to a wide range of fiber optic transceivers over a wide range of interface bandwidths. The intended use for such a high-speed LVDS buffer is to strengthen and enable PCIe signals over metal (copper) cable or metal printed circuit board (PCB) traces for large PCBs, such as backplanes, server motherboards, etc. By disposing the PCIe buffer used for metal (copper) cable between the PCIe bus and the fiber optic transceiver, one can achieve the signal conditioning and translating required to allow PCIe signals to pass over the fiber optic medium.

Claims

1. A system for transmitting and receiving a PCIe compliant signal over a fiber optic medium, comprising:

a PCIe card edge configured to receive an electronic PCIe compliant signal from a PCIe bus;

a PHY-layer translator configured to receive the electronic PCIe compliant signal from the PCIe card edge and condition the electronic PCIe compliant signal; and

a fiber optic laser module configured to receive the conditioned electronic PCIe compliant signal and convert the conditioned electronic PCIe compliant signal into a photonic PCIe compliant signal.

2. The system of claim 1, further comprising a fiber optic medium configured to carry the photonic PCIe compliant signal to a remote fiber optic laser module.

3. The system of claim 1, wherein the fiber optic laser module contains a data fiber optic laser module, and a clock fiber optic laser module.

4. The system of claim 1, wherein the electronic PCIe compliant signal is a low voltage differential signal (LVDS).

5. The system as specified in claim 1 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal without introducing latency.

6. The system as specified in claim 1 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal and mitigate jitter.

7. The system as specified in claim 1 wherein the PHY-layer translator is comprised of an equalizer configured to balance and condition the electronic PCIe complaint signal.

8. The system as specified in claim 7 wherein the equalizer is configured to both attenuate and amplify the electronic PCIe compliant signal.

9. The system of claim 1 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal in the time-domain.

10. A system for receiving a PCIe compliant signal over a fiber optic medium, comprising:

a fiber optic laser module configured to receive a photonic PCIe compliant signal and convert the photonic PCIe compliant signal into an electronic signal;

a PHY-layer translator configured to receive the electronic signal from the fiber optic laser module, and condition the electronic signal, thereby creating a conditioned electronic PCIe compliant signal; and

a PCIe card edge configured to receive the conditioned electronic PCIe compliant signal and propagate the conditioned electronic PCIe compliant signal on a PCIe bus.

11. The system of claim 10, wherein the fiber optic laser module is configured to modify PCIe signals including data (PET/PER) and clock (REFCLK).

12. The system as specified in claim 10 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal without buffering and storing the electronic PCIe compliant signal.

13. The system as specified in claim 10 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal without introducing latency.

14. The system as specified in claim 10 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal and mitigate jitter.

15. The system as specified in claim 10 wherein the PHY-layer translator is comprised of an equalizer configured to equalize the electronic PCIe complaint signal.

16. The system as specified in claim 15 wherein the equalizer is configured to both attenuate and amplify the electronic PCIe compliant signal.

17. The system as specified in claim 10 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal without buffering and storing the electronic PCIe compliant signal.

18. The system of claim 10 wherein the PHY-layer translator is configured to condition the electronic PCIe compliant signal in the time-domain.