Input output control apparatus with a plurality of ports and single protocol processing circuit

• US 8,090,893 B2
• Filed: 05/20/2010
• Issued: 01/03/2012
• Est. Priority Date: 08/12/2003
• Status: Active Grant

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Tamura, Takashi, Miyakoshi, Toshiyuki
• Primary Examiner(s): Zaman, Faisal M
• Application Number:
  US12/783,705
• Publication Number:
  US 20100228901A1
• Time in Patent Office: 593 Days
• Field of Search: 710/52, 710/305, 710/310
• US Class Current: 710/310
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

The input output control device is provided with a plurality of fiber channel interface circuits and a protocol processing circuit capable of sequentially executing the protocol processing of each port, and is provided with a reception port identification register capable of identifying the port handling data to be received and a transmission port designation register designating the port handling data to be transmitted. In addition, it is possible to provide a controller using jointly the data buffers concerned with the plurality of ports. Control of a plurality of fiber channel interfaces with a low component count is possible, as is also the provision of an input output control device making an adequate capacity distribution with respect to the protocol processing between the plural fiber channel interfaces.

Claims

1. An input/output (I/O) control device, to which an I/O request originated in a host is communicated via a Peripheral Component Interconnect (PCI) interface, controlling a plurality of fibre channel interfaces for transmitting and receiving data corresponding to said I/O request in units of frames, said I/O control device comprising:

a plurality of ports each having interface control circuits controlling said fibre channel interfaces independently with each of the other ports;

a common received data buffer, being divided into a plurality of entries, storing frame data received by said plurality of ports, being directly connected with all of the interface control circuits through receive data lines;

a common transmitted data buffer, being divided into a plurality of entries, storing frame data to be transmitted to said plurality of ports, being directly connected with all of the interface control circuits through a transmit data line;

a single protocol processing circuit, to process collectively a plurality of protocols executed on said plurality of interfaces, carrying out processing of the frame data in said common transmitted data buffer and said common received data buffer;

a transmission buffer entry number register for the setting, by said single protocol processing circuit, a buffer entry number of said common transmitted data buffer to which the frame data to be transmitted is stored;

a transmission port number register for the setting, by said single protocol processing circuit, a port number of the port transmitting the frame data to be transmitted; and

a decoding circuit generating, when said single protocol processing circuit has emitted a transmission instruction, a transmission instruction signal, from the contents of said transmission port number register, to the designated interface control circuit through one of a plurality of transmission command decoding lines, each transmission command decoding line being directly connected with each interface control circuit,

wherein each interface control circuit comprises;

a transmission stack reading out and storing the contents of said transmission buffer entry number register, after said interface control circuit has received said transmission instruction signal, and

a frame generation circuit sequentially reading out the transmission buffer entry number information stored in said transmission stack, reading out the corresponding transmission data from said common transmitted data buffer through said transmit data line, and generating transmission frames.