Architectures for supporting communication and access between multiple host devices and one or more common functions

• US 8,090,894 B1
• Filed: 09/21/2007
• Issued: 01/03/2012
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Khodabandehlou, Hamid, Raza, Syed Babar, Nayak, Anup
• Primary Examiner(s): STIGLIC, RYAN M
• Application Number:
  US11/903,271
• Time in Patent Office: 1,565 Days
• Field of Search: 710/313
• US Class Current: 710/313
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

A controller circuit can provide communication paths between multiple host devices and at least one function interface (I/F), where a function I/F can allow access to a predetermined circuit function. The controller circuit can include an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a predetermined data transmission protocol and a data switching circuit coupled to the endpoint point buffer circuit. The data switching circuit is configurable to provide communication paths that enable a first host I/F and a second host I/F to access at least a same function I/F, and enable the first and second host I/Fs to communicate with one another.

Claims

1. A controller circuit comprising:

an endpoint buffer circuit having a plurality of storage locations configurable as endpoints according to a USB protocol; and

a data switching circuit coupled to the endpoint buffer circuit configurable to provide communication paths that enable a first host interface (I/F) and a second host I/F to access at least an individual function I/F of one or more function I/Fs of the controller circuit configured to allow access to at least one predetermined circuit function, and to enable first and second host I/F'"'"'s to communicate with one another, wherein the communication paths include a first communication path that enables the first host I/F to access at least the individual function I/F without passing through the second host I/F and a second communication path that enables the second host I/F to access at least the individual function I/F without passing through the first host I/F, and wherein the data switching circuit comprises a multiplexer (MUX) and a de-multiplexer (DE-MUX) coupled to the endpoint buffer circuit, the second host I/F and the at least one individual function I/F to selectively provide the communication paths.

2. The controller circuit of claim 1, wherein:

the individual function I/F is coupled to any selected from the group consisting of a storage device or input/output device.

3. The controller circuit of claim 1, wherein:

the data switching circuit can include any selected from the group consisting of a shared data bus or the multiplexer selectively accessible by at least the second host I/F and the individual function I/F.

4. The controller circuit of claim 1, wherein:

the controller circuit is configurable to provide a first host-to-second host transmission path that includes portions of the data switching circuit and portions of the endpoint buffer circuit.

5. The controller circuit of claim 1, wherein:

the controller circuit is configurable to provide a third communication path between the individual function I/F and both the first host I/F and the second host I/F that includes portions of the data switching circuit and portions of the endpoint buffer circuit.

6. The controller circuit of claim 1, wherein:

the at least one function I/F comprises a plurality of function I/Fs that are each configurable to provide one or more signals for accessing at least one different predetermined function, the controller circuit being configurable to provide an individual first host I/F communication path between the first host I/F and at least two of the plurality of function I/Fs.

7. The controller circuit of claim 1, wherein:

the at least one function I/F comprises a plurality of function I/Fs that are each configurable to provide one or more signals for accessing at least one different predetermined function, the controller being configurable to provide an individual second host I/F communication path between the second host I/F and at least two of the plurality of function I/Fs.

8. The controller circuit of claim 1, wherein:

the endpoint buffer circuit is configurable to have at least one physical endpoint corresponding to an endpoint identification value of the USB protocol; and

the data switching circuit is configurable to provide at least two different communication paths from the one physical endpoint as different logical endpoints corresponding to the one physical endpoint.

9. The controller circuit of claim 1, wherein:

the individual function I/F is programmable between at least two different function I/Fs, each different function I/F enabling access to at least one other predetermined circuit function.

10. The controller circuit of claim 9, wherein:

the at least two different functions include accesses to different types of solid state storage media.

11. The controller circuit of claim 1, wherein:

the second host I/F is programmable between at least two different configured host I/Fs, each different configured host I/F enabling communication with a different type of host.

12. The controller circuit of claim 1, further including:

a processor coupled to a memory and configurable to execute instructions stored in the memory and outputs configuration data; and

wherein the data switching circuit is configurable according to the configuration data.

13. The controller circuit of claim 1, wherein the first host I/F comprises:

an endpoint detector configurable to determine an endpoint value of a communication received at the first host I/F, and

a response circuit coupled to the endpoint detector and configurable to receive endpoint status information, the response circuit providing a predetermined indication when the endpoint value corresponds to an endpoint indicated as in use by at least one function I/F of the one or more function I/Fs or the second host I/F by the endpoint status information.

14. The controller circuit of claim 1, wherein:

the data switching circuit is configurable to provide a control communication path between the first host I/F and a control endpoint, and at the same time, the second communication path.

15. The controller circuit of claim 1, further including:

a processor circuit configurable to execute instructions stored in a processor memory and outputs configuration data, the processor memory being coupled to any selected from the group of;

the first host I/F, the second host I/F, or at least one of the one or more function I/Fs; and

wherein the data switching circuit is configurable according to the configuration data.

16. The controller circuit of claim 1, further including:

a timing circuit for generating a timing signal for the controller circuit, the timing circuit comprising at least one crystal input operable for receiving a crystal; and

an oscillator circuit for generating an oscillating signal according to a crystal at the at least one crystal input, the oscillator circuit configured to accommodate any of a plurality of crystals of different resonance frequencies.

17. A method comprising the steps of:

in one integrated circuit,

providing at least a first data communication path between a first host interface (I/F) and at least a first endpoint storage location;

providing a second data communication path between the first host I/F and a second endpoint storage location;

configuring the second communication data path between the second endpoint storage location and a controller; and

configuring a third data communication path between at least the first endpoint storage location and a second host I/F and between at least the first endpoint storage location and a function I/F, wherein the second host I/F is programmable to accommodate different interface types, and wherein the function I/F is programmable to provide access to one or both of;

different types of functions or different versions of an individual function, and wherein the second data communication path and the third data communication path can be utilized simultaneously.

18. The method of claim 17, further including:

in a communication between the first host I/F and the second host I/F or a transfer between the first host I/F and the function I/F, storing data in at least one endpoint storage location configured for the direction of communication.

19. The method of claim 18, wherein:

in a communication between the second host I/F and the function I/F, storing data in at least one endpoint storage location configured for in a first direction, and

switching the direction of the endpoint storage location.

20. The method of claim 17, wherein:

configuring the data communication path includes creating predetermined signal paths according to configuration information output from a processor that executes instructions in an instruction memory; and

in a configuration operation, loading instruction data into the instruction memory from one or more of;

the first host I/F, the second host I/F, or the at least one function I/F.

21. A controller circuit device, comprising:

an integrated circuit substrate that includes

a first host interface (I/F) operable to communicate with a first type host device, a second host I/F operable to communicate with a second type host device, and at least one function I/F operable to communicate with at least one predetermined function; and

a control and memory circuit configurable to provide a plurality of communication paths, including at least a first host I/F to second host I/F path that includes a portion of an endpoint buffer memory but does not include the at least one function I/F, a first host I/F to function I/F path that includes a portion of the endpoint buffer memory but does not include the second host I/F, and a second host I/F to function I/F path that includes a portion of the endpoint buffer memory but does not include the first host I/F, and further comprising a multiplexer (MUX) and a de-multiplexer (DE-MUX) coupled to the endpoint buffer memory, the second host I/F and the at least one function I/F to selectively provide at least some of the plurality of communication paths.

22. The controller circuit device of claim 21, wherein:

the first host I/F is a universal serial bus (USB) I/F.