System and method for simulating an aspect of a memory circuit

• US 8,090,897 B2
• Filed: 06/12/2007
• Issued: 01/03/2012
• Est. Priority Date: 07/31/2006
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Rajan, Suresh Natarajan, Schakel, Keith R., Smith, Michael John Sebastian, Wang, David T., Weber, Frederick Daniel
• Primary Examiner(s): Le, Vu
• Application Number:
  US11/762,013
• Publication Number:
  US 20080062773A1
• Time in Patent Office: 1,666 Days
• Field of Search: 711/103, 711/110, 711/105, 711/106, 713/500
• US Class Current: 711/103
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40618 Refresh operations over multiple banks or interleaving
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.

Claims

1. A sub-system, comprising:

an interface circuit operable for receiving, from a system, write data to be stored on a first memory circuit and for communicating the write data to the first memory circuit, the first memory circuit having a first latency for the write data,

wherein the interface circuit is further operable to;

cause the first memory circuit to appear to the system as a second memory circuit having a second latency for the write data, the second latency being different than the first latency; and

time shift communication of the write data to the first memory circuit by an amount of time equal to a difference between the first latency and the second latency, where the difference between the first latency and the second latency is equal to or greater than one clock cycle, and where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC.

2. The sub-system of claim 1, wherein the at latency includes a first column address strobe (CAS) latency and the second latency includes a second CAS latency.

3. The sub-system of claim 2, wherein the second CAS latency is longer than the first CAS latency.

4. The sub-system of claim 1, wherein the first latency includes the first tRCD, the second latency includes the second tRCD, and the second tRCD is longer than the first tRCD.

5. The sub-system of claim 1, wherein the the first latency includes the first tRP, the second latency includes the second tRP, and second tRP is longer than the first tRP.

6. The sub-system of claim 1, wherein the first memory circuit is a dynamic random access memory (DRAM).

8. The sub-system of claim 1, wherein the first latency is longer than the second latency.

9. The sub-system of claim 1, wherein each of the first latency and the second latency comprises a write latency.

10. The sub-system of claim 1, wherein the interface circuit is adapted for coupling with a plurality of first memory circuits, each first memory circuit having the first latency for the write data, and

wherein the interface circuit is operable to advance or delay communication of the write data to at least one of the first memory circuits by the amount of time equal to the difference between the first latency and the second latency.

11. The sub-system of claim 1, wherein the first memory circuit comprises a plurality of first memory devices and the interface circuit is operable to cause the plurality of first memory devices to appear to the system as a single second memory circuit having the second latency for the write data.

12. The sub-system of claim 1, wherein the first memory circuit comprises a plurality of first memory devices and the interface circuit is operable to cause the plurality of first memory devices to appear to the system as a plurality of second memory devices, each second memory device having the second latency for the write data, and

wherein a number of the second memory devices is less than a number of the first memory circuits.

13. The sub-system of claim 1, wherein the first memory circuit comprises memory devices each having a first memory capacity and the second memory circuit comprises memory devices each having a second memory capacity that is greater than the first memory capacity.

19. The sub-system of claim 1, wherein the first latency includes the first tRAS and the second latency includes the second tRAS.

20. The sub-system of claim 1, wherein the first latency includes the first tRC and the second latency includes the second tRC.

7. A system, comprising:

a first memory circuit; and

an interface circuit in communication with the first memory circuit and a system device, the interface circuit operable to receive, from the system device, write data to be stored on the first memory circuit,

wherein the first memory circuit has a first latency for the write data, and

the interface circuit is further operable to;

cause the first memory circuit to appear to the system device as a second memory circuit having a second latency for the write data, the second latency being different than the first latency; and

time shift communication of the write data to the first memory circuit by an amount of time equal to a difference between the first latency and the second latency, where the difference between the first latency and the second latency is equal to or greater than one clock cycle, and where the first latency includes at least one of a first row address strobe to column address strobe latency (tRCD), a first row precharge latency (tRP), a first activate to precharge latency (tRAS), or a first row cycle time (tRC), and the second latency includes at least one of a second tRCD, a second tRP, a second tRAS, or a second tRC.

14. The system of claim 7, wherein the first latency includes the first tRCD, the second latency includes the second tRCD, and the second tRCD is longer than the first tRCD.

15. The system of claim 7, wherein the first latency includes the first tRP, the second latency includes the second tRP, and the second tRP is longer than the first tRP.

16. The system of claim 7, wherein the first latency includes the first tRAS and the second latency includes the second tRAS.

17. The system of claim 7, wherein the first latency includes the first tRC and the second latency includes the second tRC.

18. The system of claim 7, wherein the first memory circuit is a DRAM.