Manufacturing method of semiconductor device
First Claim
1. A manufacturing method of a semiconductor device comprising:
- a processing mask layer forming step of forming a processing mask layer comprising at least one layer applied on a target layer and hardened by a heat hardening treatment, and performing hardening treatment for at least one layer in said processing mask layer;
a processing mask layer etching step of applying a resist layer for exposure to said processing mask layer after the processing mask layer forming step, exposing and developing the resist layer to form a resist pattern, and etching said processing mask layer using said resist pattern as a mask; and
a target layer etching step of etching said target layer using a pattern of said processing mask layer formed at said processing mask layer etching step as a mask, and wherein the hardening treatment uses an implantation process for implanting a predetermined atom, a reducing plasma treatment, or a treatment for applying UV or electron beam.
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Accused Products
Abstract
It is an object of the present invention to provide a method of manufacturing a semiconductor device that reduces the deterioration in processed configuration and the pattern roughness of a film to be processed, and is close to the original design and applicable to a dual damascene step and the like. The manufacturing method comprises a processing mask layer forming step of forming a processing mask layer (a lower organic film and a middle layer) comprising at least one film, and hardening treatment for at least one film of the processing mask layer by applying a film and heat hardening treatment; a processing mask layer etching step of applying a resist film for exposure to the processing mask layer, exposing and developing it to form a resist pattern, and etching the processing mask layer using the resist pattern as a mask; and a film to be processed etching step of etching the film to be processed using the pattern of the processing mask layer formed at the processing mask layer etching step as a mask.
33 Citations
18 Claims
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1. A manufacturing method of a semiconductor device comprising:
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a processing mask layer forming step of forming a processing mask layer comprising at least one layer applied on a target layer and hardened by a heat hardening treatment, and performing hardening treatment for at least one layer in said processing mask layer; a processing mask layer etching step of applying a resist layer for exposure to said processing mask layer after the processing mask layer forming step, exposing and developing the resist layer to form a resist pattern, and etching said processing mask layer using said resist pattern as a mask; and a target layer etching step of etching said target layer using a pattern of said processing mask layer formed at said processing mask layer etching step as a mask, and wherein the hardening treatment uses an implantation process for implanting a predetermined atom, a reducing plasma treatment, or a treatment for applying UV or electron beam. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A manufacturing method of a semiconductor device forming a dual damascene structure on a semiconductor substrate comprising:
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an opening step of opening a via hole in a low dielectric layer formed on a lower wiring layer; a lower organic layer forming step of applying a lower organic layer on said low dielectric layer and burying said lower organic layer in said via hole; a middle layer forming step of forming a middle layer containing silicon oxide on said lower organic layer; a resist pattern forming step of applying a resist layer on the middle layer and exposing and developing the resist layer to form a resist pattern of a trench; a middle layer etching step of etching said middle layer using said resist pattern as a mask; a lower organic layer etching step of etching said lower organic layer using a pattern of said middle layer formed at said middle layer etching step as a mask; a trench forming step of etching said low dielectric layer using a pattern of said lower organic layer formed at said lower organic layer etching step as a mask and forming said trench having a depth not reaching a bottom of said via hole; and a wiring layer forming step of removing a film existing in said via hole on said lower wiring layer and burying a wiring layer material in said via hole and said trench, wherein a hardening treatment is performed for at least one of said lower organic layer and said middle layer before the resist pattern forming step, and wherein the hardening treatment uses an implantation process for implanting a predetermined atom, a reducing plasma treatment, or a treatment for applying UV treatment or electron beam. - View Dependent Claims (18)
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Specification