Non-volatile semiconductor memory device and depletion-type MOS transistor

• US 8,093,664 B2
• Filed: 01/26/2009
• Issued: 01/10/2012
• Est. Priority Date: 02/29/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Gomikawa, Kenji, Noguchi, Mitsuhiro
• Primary Examiner(s): STARK, JARRETT J
• Application Number:
  US12/359,643
• Publication Number:
  US 20090218637A1
• Time in Patent Office: 1,079 Days
• Field of Search: 257/402, 257/403, 257/344, 257/E29.062, 257/E29.255
• US Class Current: 257/403
• CPC Class Codes: H01L 29/7838 without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

A peripheral circuit includes at least a first transistor. The first transistor comprises a gate electrode formed on a surface of a semiconductor layer via a gate insulating film. A channel region of a first conductivity type having a first impurity concentration is formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode. A source-drain diffusion region of the first conductivity type is formed on the surface of the semiconductor layer to sandwich the gate electrode and has a second impurity concentration greater than the first impurity concentration. An overlapping region of the first conductivity type is formed on the surface of the semiconductor layer directly below the gate electrode where the channel region and the source-drain diffusion region overlap. The overlapping region has a third impurity concentration greater than the second impurity concentration.

Claims

1. A non-volatile semiconductor memory device, comprising:

a memory cell array including memory cell transistors arranged therein, the memory cell transistors being provided with a charge accumulation layer formed on a semiconductor substrate via a gate insulating film; and

a peripheral circuit configured to drive the memory cell transistors, the peripheral circuit including at least a first transistor,

the first transistor further comprising;

a semiconductor layer of a second conductivity type;

a first gate electrode formed on a surface of the semiconductor layer via the gate insulating film;

a first channel region of a first conductivity type having a first impurity concentration and formed on a surface of the semiconductor layer directly below and in the vicinity of the first gate electrode, the first conductivity type being of the opposite conduction type to the second conductivity type;

first source-drain regions of the first conductivity type having a second impurity concentration which is greater than the first impurity concentration and formed on the surface of the semiconductor layer;

contact regions of the first conductivity type having a fourth impurity concentration which is greater than the second impurity concentration and formed on at least a portion of a surface of the first source-drain regions; and

overlapping regions of the first conductivity type having a third impurity concentration which is greater than the second impurity concentration and formed on the surface of the semiconductor layer directly below and in the vicinity of the gate electrode where the channel region and the source-drain regions overlap, the contact regions each being formed in a position more distant from the first gate electrode than respective one of the overlapping regions, with the respective one of the first source-drain regions interposed therebetween.

2. The non-volatile semiconductor memory device according to claim 1, wherein an impurity implanted in the first channel region and an impurity implanted in the first source-drain regions are of different elements.

3. The non-volatile semiconductor memory device according to claim 2, wherein an impurity implanted in the first channel region is arsenic (As) and an impurity implanted in the first source-drain regions is phosphorus (P).

4. The non-volatile semiconductor memory device according to claim 1, wherein the peripheral circuit further comprises second transistors, the second transistors each comprising:

a gate electrode electrically connected to a drain of the first transistor; and

a source electrically connected to plural gates of the memory cell transistors, wherein

the first transistor is depletion-type (D-type).

5. The non-volatile semiconductor memory device according to claim 1, wherein the first source-drain regions are formed in a self-aligning manner with respect to the gate electrode.

6. The non-volatile semiconductor memory device according to claim 1, wherein the peripheral circuit further comprises a second transistor in addition to the first transistor, the second transistor comprising:

a second gate electrode formed on the surface of the semiconductor layer via the gate insulating film;

a second channel region of the first conductivity type having a fifth impurity concentration and formed on a surface of the semiconductor layer including directly below the second gate electrode; and

second source-drain regions of the first conductivity type having a sixth impurity concentration greater than the fifth impurity concentration.

7. The non-volatile semiconductor memory device according to claim 6, wherein an impurity implanted in the first channel region and the second channel region, and an impurity implanted in the first source-drain regions and the second source-drain regions are of different elements.

8. The non-volatile semiconductor memory device according to claim 6, wherein the first impurity concentration and the fifth impurity concentration are the same, and the third impurity concentration and the sixth impurity concentration are the same.

14. The non-volatile semiconductor memory device according to claim 6, wherein the peripheral circuit further comprises third transistors, the third transistors each comprising:

a gate electrode electrically connected to a drain of the first transistor; and

a source electrically connected to plural gates of the memory cell transistors.

15. The non-volatile semiconductor memory device according to claim 1, wherein the overlapping regions each protrudes past edges of the gate electrode by 10 nm-1 um in a direction parallel to a substrate.

9. A depletion-type MOS transistor, comprising:

a semiconductor layer of a second conductivity type;

a gate electrode formed on a surface of the semiconductor layer via a gate insulating film;

a channel region of a first conductivity type having a first impurity concentration and formed on a surface of the semiconductor layer directly below and in the vicinity of the gate electrode, the first conductivity type being of the opposite conduction type to the second conductivity type;

source-drain regions of the first conductivity type having a second impurity concentration which is greater than the first impurity concentration and formed on the surface of the semiconductor layer;

contact regions of the first conductivity type having a fourth impurity concentration which is greater than the second impurity concentration and formed on at least a portion of a surface of the source-drain regions; and

overlapping regions of the first conductivity type having a third impurity concentration which is greater than the second impurity concentration and formed on the surface of the semiconductor layer directly below and in the vicinity of the gate electrode where the channel region and the source-drain region overlap, the contact regions each being formed in a position more distant from the first gate electrode than respective one of the overlapping regions, with the respective one of the source-drain regions interposed therebetween.

10. The depletion-type MOS transistor according to claim 9, wherein an impurity implanted in the channel region and an impurity implanted in the source-drain regions are of different elements.

11. The depletion-type MOS transistor according to claim 10, wherein an impurity implanted in the channel region is arsenic (As) and an impurity implanted in the source-drain regions is phosphorus (P).

12. The depletion-type MOS transistor according to claim 9, wherein the source-drain regions are formed in a self-aligning manner with respect to the gate electrode.

13. The non-volatile semiconductor memory device according to claim 9, wherein the overlapping regions each protrudes past edges of the gate electrode by 10 nm-1 um in a direction parallel to a substrate.