Chip package and manufacturing method thereof

• US 8,093,690 B2
• Filed: 03/31/2009
• Issued: 01/10/2012
• Est. Priority Date: 10/31/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Ko, Dongkyun, Lee, Jung, An, Jaesun
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US12/414,996
• Publication Number:
  US 20100109132A1
• Time in Patent Office: 1,015 Days
• Field of Search: 257/659, 257/660
• US Class Current: 257/660
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15313 : being a land array, e.g. LGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H05K 1/0218 : by printed shielding conductors, ground planes or power plane H05K1/0236 takes precedence
• CPC Class Codes: H05K 2203/0415 : Small preforms other than balls, e.g. discs, cylinders or pillars
• CPC Class Codes: H05K 3/0032 : of organic insulating material
• CPC Class Codes: H05K 3/0052 : Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/284 : for encapsulating mounted components H05K1/185 takes precedence

Abstract

A chip package including a shielding layer having a plurality of conductive connectors for better electromagnetic interferences shielding is provided. The conductive connectors can be flexibly arranged within the molding compound for better shielding performance. The shielding layer having the conductive connectors functions as the EMI shield and the shielding layer is electrically grounded within the package structure.

Claims

1. A chip package, comprising:

a substrate;

at least a chip disposed on the substrate and electrically connected to the substrate;

a molding compound disposed over the substrate, at least encapsulating the chip, and a portion of the substrate; and

a shield including;

a plurality of conductive connectors circumscribing a lateral periphery of the molding compound, wherein a side surface of at least one of the plurality of conductive connectors is exposed, and wherein the at least one of the conductive connectors is connected to the substrate; and

a first portion disposed over portions of the molding compound, wherein the first portion is electrically connected to the conductive connectors;

wherein the side surface of the at least one of the plurality of conductive connectors is exposed at an external periphery of the shield, and is inwardly indented such that the external periphery of the shield is inwardly indented.

2. The chip package as claimed in claim 1, wherein the conductive connectors are individual conductive vias, separate from one another and partially exposed from the molding compound.

3. The chip package as claimed in claim 2, wherein at least one of the conductive vias has an exposed side surface.

4. The chip package as claimed in claim 1, wherein:

the side surface of the at least one of the plurality of conductive connectors extends from a first part of the lateral periphery of the molding compound to a second part of the lateral periphery of the molding compound.

5. The chip package as claimed in claim 3, wherein at least one of the exposed conductive vias has an exposed upper surface.

6. The chip package as claimed in claim 1, wherein the plurality of conductive connectors provide at least partial EMI shielding.

7. The chip package as claimed in claim 1, wherein a subset of the plurality of conductive connectors provide at least partial EMI shielding.

8. The chip package as claimed in claim 1, further comprising a ground path extending from a lower surface of the substrate to the shield.

9. A semiconductor package comprising:

a substrate;

a chip attached to the substrate;

a package body encapsulating the chip; and

a shield including;

a first portion disposed on an exterior upper surface of the package body; and

a plurality of conductive vias circumscribing the chip, at least one of the plurality of conductive vias having a side surface that is exposed;

wherein the first portion is electrically connected to the substrate through the plurality of conductive vias;

wherein the side surface of the at least one of the plurality of conductive vias is exposed at an external periphery of the shield, and is inwardly indented such that the external periphery of the shield is inwardly indented.

10. The semiconductor package as claimed in claim 9, wherein:

the side surface of the at least one of the plurality of conductive vias extends laterally from a first part of an exterior lateral surface of the package body to a second part of the exterior lateral surface of the package body.

11. The semiconductor package as claimed in claim 9, Wherein at least one of the plurality of conductive vias is located within the package body.

13. The semiconductor package as claimed in claim 9, further comprising:

a ground path extending from a lower surface of the substrate to the first portion of the shield.

12. The semiconductor package as claimed in 9, wherein the plurality of conductive vias include at least one plated via structure.

14. A semiconductor package comprising:

a substrate including at least one ground via;

a semiconductor die disposed on the substrate;

a package body encapsulating the die, the package body having an upper surface; and

a shield including;

a first portion disposed on the upper surface of the package body; and

a lateral portion including a plurality of conductive vias extending from the first portion to the substrate and circumscribing the semiconductor die, wherein at least one of the plurality of conductive vias includes a side surface that is exposed;

wherein the first portion is electrically connected to the lateral portion;

wherein the side surface of the at least one of the plurality of conductive vias is exposed at an external periphery of the shield, and is inwardly indented such that the external periphery of the shield is inwardly indented.

15. The semiconductor package as claimed in claim 14, wherein the plurality of conductive vias extend from an upper surface of the substrate to the upper surface of the package body.

16. The semiconductor package as claimed in claim 14, wherein:

at least one of the plurality of conductive vias is electrically connected to a corresponding ground via; and

the shield is electrically connected to the substrate through the plurality of conductive vias and the corresponding ground via.

17. The semiconductor package as claimed in claim 14, wherein the lateral portion of the shield is disposed on at least one lateral surface of the package body and electrically connected to at least one of the plurality of conductive vias.

18. The semiconductor package as claimed in claim 14, wherein:

the side surface of the at least one of the plurality of conductive vias extends from a first part of a lateral surface of the package body to a second part of the lateral surface of the package body.