In situ verification of capacitive power support

• US 8,093,868 B2
• Filed: 09/04/2008
• Issued: 01/10/2012
• Est. Priority Date: 09/04/2008
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cagno, Brian J., Elliott, John C., Kubo, Robert A., Lucas, Gregg S.
• Primary Examiner(s): TSO, EDWARD H
• Application Number:
  US12/204,456
• Publication Number:
  US 20100052625A1
• Time in Patent Office: 1,223 Days
• Field of Search: 320/107, 320/128, 320/137, 320/166, 320/167, 365/201, 365/227, 365/228, 365/229, 714/24, 714/25, 714/718, 713/324
• US Class Current: 320/167
• CPC Class Codes: G01R 31/387 Determining ampere-hour charge capacity or SoC
• CPC Class Codes: G01R 31/64 Testing of capacitors
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2228 Battery-backed RAM
• CPC Class Codes: H02J 7/345 using capacitors as storage or buffering devices

Abstract

A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested.

Claims

1. A computer program product comprising a computer recordable medium having a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:

charge a super capacitor to a first voltage level by setting a voltage regulator output to the first voltage level, wherein the voltage regulator provides power to a memory system;

set the voltage regulator output to a second voltage level such that the memory system continues to operate at the second voltage level;

monitor and record voltage and current discharge values at the super capacitor at regular intervals until a test period expires;

calculate a capacitance of the super capacitor based on the recorded voltage and current discharge values; and

determine whether the capacitance of the super capacitor will support hardening of cache data from a volatile memory to a non-volatile memory in the memory system in response to a power event.

2. The computer program product of claim 1, wherein the voltage regulator charges the super capacitor.

3. The computer program product of claim 2, wherein charging the super capacitor to a first voltage level comprises:

configuring the voltage regulator to provide a maximum voltage that can be tolerated by a system that the voltage regulator supports.

4. The computer program product of claim 3, wherein charging the super capacitor to a first voltage level further comprises:

waiting a period of time to stabilize the super capacitor voltage to the first voltage level.

5. The computer program product of claim 1, wherein setting the voltage regulator output to a second voltage level further comprises:

configuring the voltage regulator to provide a minimum voltage at which the system can still operate without failure.

6. The computer program product of claim 1, wherein the time period is a predetermined amount of time.

7. The computer program product of claim 1, wherein the time period is an amount of time it takes for the super capacitor to discharge from the first voltage level to a predetermined second voltage level.

8. The computer program product of claim 1, wherein the super capacitor is a main super capacitor and wherein the computer readable program further causes the computing device to:

responsive to a determination that the capacitance of the super capacitor will not support hardening of cache data from the volatile memory to the non-volatile memory, fail over to a failover super capacitor.

9. The computer program product of claim 8, wherein the computer readable program further causes the computing device to:

charge the failover super capacitor to the first voltage level by setting the voltage regulator output to the first voltage level;

set the voltage regulator output to the second voltage level;

monitor and record voltage and current discharge values at the failover super capacitor at regular intervals until the test period expires;

calculate a capacitance of the failover super capacitor based on the recorded voltage and current discharge values; and

determine whether the capacitance of the failover super capacitor will support hardening of cache data from the volatile memory to the non-volatile memory in the memory system in response to a power event.

10. The computer program product of claim 8, wherein failing over to the failover super capacitor comprises:

disabling a field effect transistor between the voltage regulator and the main super capacitor and enabling a field effect transistor between the voltage regulator and the failover super capacitor.

11. A method, in a data processing system, for in situ verification of capacitive power support, the method comprising:

charging a super capacitor to a first voltage level by setting a voltage regulator output to the first voltage level, wherein the voltage regulator provides power to a memory system;

setting voltage regulator output to a second voltage level such that the memory system continues to operate at the second voltage level;

monitoring and recording voltage and current discharge values at the super capacitor at regular intervals until a test period expires;

calculating a capacitance of the super capacitor based on the recorded voltage and current discharge values; and

determining whether the capacitance of the super capacitor will support hardening of cache data from a volatile memory to a non-volatile memory in response to a power event.

12. The method of claim 11, wherein the voltage regulator charges the super capacitor.

13. The method of claim 12, wherein charging the super capacitor to a first voltage level comprises:

configuring the voltage regulator to provide a maximum voltage that can be tolerated by a system that the voltage regulator supports.

14. The method of claim 13, wherein charging the super capacitor to a first voltage level further comprises:

waiting a period of time to stabilize the super capacitor voltage to the first voltage level.

15. The method of claim 12, wherein setting the voltage regulator output to a second voltage level further comprises:

configuring the voltage regulator to provide a minimum voltage at which the system can still operate without failure.

16. The method of claim 11, wherein the time period is a predetermined amount of time.

17. The method of claim 11, wherein the time period is an amount of time it takes for the super capacitor to discharge from the first voltage level to a predetermined second voltage level.

18. A memory system comprising:

a controller, wherein the controller is configured to detect a power event from a voltage regulator that provides power to a storage controller and the memory system;

a volatile memory; and

a non-volatile memory, wherein the non-volatile memory is used to harden cache data from the volatile memory for a storage controller responsive to the power event;

wherein the controller is configured to charge a super capacitor to a first voltage level by setting a voltage regulator output to the first voltage level, set the voltage regulator output to a second voltage level such that the memory system continues to operate at the second voltage level, monitor and record voltage and current discharge values at the super capacitor at regular intervals until a test period expires, calculate a capacitance of the super capacitor based on the recorded voltage and current discharge values, and determine whether the capacitance of the super capacitor will support hardening of cache data from a volatile memory to a non-volatile memory in response to a power event.

19. The memory system of claim 18, wherein the voltage regulator charges the super capacitor and wherein charging the super capacitor to a first voltage level comprises:

configuring the voltage regulator to provide a maximum voltage that can be tolerated by a system that the voltage regulator supports;

waiting a period of time to stabilize the super capacitor voltage to the first voltage level.

20. The memory system of claim 18, wherein setting the voltage regulator output to a second voltage level further comprises:

configuring the voltage regulator to provide a minimum voltage at which the system can still operate without failure.