Configurable IC having a routing fabric with storage elements

• US 8,093,922 B2
• Filed: 04/06/2009
• Issued: 01/10/2012
• Est. Priority Date: 03/20/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Schmit, Herman, Huang, Randy Renfu
• Primary Examiner(s): LE, DON P
• Application Number:
  US12/419,289
• Publication Number:
  US 20100001759A1
• Time in Patent Office: 1,009 Days
• Field of Search: 326 37- 41, 326/46
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

Claims

1. A method comprising:

storing a first signal along a particular path of a routing fabric that directly connects a first circuit of an integrated circuit (“

IC”

) to a second circuit of the IC; and

while storing said first signal along the particular path, passing a second signal from the first circuit to the second circuit along the particular path.

2. The method of claim 1 further comprising passing the first signal to the second circuit at a clock cycle subsequent to the passing of the second signal.

3. The method of claim 2, wherein said clock cycle is a sub-cycle clock of a user defined clock.

4. The method of claim 1 further comprising receiving the first signal at an input of the first circuit from a feedback loop established with the particular path, wherein said receiving occurs while the second signal is passed to the second circuit.

5. The method of claim 4 further comprising, after passing the second signal, passing the first signal from the first circuit to the second circuit along the particular path.

6. The method of claim 5, wherein said passing of the first signal occurs one clock cycle after passing the second signal.

7. The method of claim 5, wherein said passing of the first signal occurs at least two clock cycles after passing said second signal to the second circuit.

8. The method of claim 1, wherein said particular path comprises parallel paths directly connecting said first circuit to said second circuit, wherein a storage element for storing said first signal is located along one of said parallel paths.

9. A method comprising:

receiving a first signal at a storage element located along a particular path within a routing fabric of an integrated circuit (“

IC”

), said particular path for directly connecting a first circuit of the IC to a second circuit of the IC;

storing said first signal at the storage element; and

transparently routing a second signal from the first circuit to the second circuit through the particular path while said storage element stores said first signal.

10. The method of claim 9 further comprising transparently routing the first signal from the storage element circuit to a third circuit.

11. The method of claim 9 further comprising routing the first signal from the storage element to the second circuit.

12. The method of claim 11 further comprising receiving the first signal at the storage element for routing to a third circuit.

13. The method of claim 9, wherein storing the first signal comprises configurably storing the first signal based on configuration data received at the storage element.

14. The method of claim 9, wherein said particular path comprises parallel paths directly connecting said first circuit to said second circuit, wherein said storage element is located along one of said parallel paths.

15. The method of claim 9, wherein the first circuit is a logic circuit for producing a logic output and said first signal is a first output signal of the logic circuit and said second signal is a second output signal of the logic circuit.

16. The method of claim 9, wherein the first circuit is an interconnect circuit for routing signals from at least two different circuits of the IC to said second circuit.

17. An integrated circuit (“

IC”

) comprising;

a) a source circuit comprising at least one output;

b) a destination circuit comprising at least one input; and

c) a routing fabric comprising a plurality of wiring paths for passing signals between circuits of the IC, said routing fabric comprising a particular wiring path connecting the output of the source circuit to the input of the destination circuit,

wherein the particular wiring path comprises a first path and a second path that is parallel to said first path, said first path for configurably storing a first output signal of the source circuit while said second path routes a second output signal of the source circuit to the destination circuit.

18. The IC of claim 17, wherein said first path comprises a storage element for configurably storing said first output signal.

19. The IC of claim 18 further comprising a configuration data storage for storing configuration data that is supplied to the storage element to configure said storage element to store said first output signal.

20. The IC of claim 18, wherein said first path directly connects said output of the source circuit to an input of the storage element and directly connects an output of said storage element to said input of the destination circuit.

21. The IC of claim 20, wherein said second path directly connects said output of the source circuit to another input of the destination circuit.

22. The IC of claim 17, wherein said source circuit is a configurable interconnect circuit for configurably routing signals to said destination circuit based on configuration data received by said source circuit.

23. An integrated circuit (“

IC”

) comprising;

a) a destination circuit comprising at least one input;

b) an interconnect circuit comprising a plurality of inputs and an output stage for routing a signal from a selected input of the interconnect circuit to the input of said destination circuit, said output stage comprising a first storage element for configurably storing said signal from said selected input before said signal is supplied to the input of the destination circuit; and

c) a second storage element for receiving said signal from the first storage element and storing said signal before supplying said signal to one of the inputs of the interconnect circuit.

24. The IC of claim 23, wherein operations of the first storage element and the second storage element are based on a configuration data.

25. The IC of claim 24, wherein the operation of the first storage element is determined by a first signal derived from the configuration data and the operation of the second storage element is determined by a second signal derived from the configuration data, wherein the second signal is at an opposite polarity as the first signal.

26. The IC of claim 23, wherein the interconnect circuit further comprises a plurality of select lines for selecting an input from the plurality of inputs for said output stage to route to the input of the destination circuit.

27. The IC of claim 23, wherein the interconnect circuit is a configurable interconnect circuit.

28. The IC of claim 23, wherein the second storage element configurably stores said signal before supplying said signal to the input of the interconnect circuit.

29. An integrated circuit (“

IC”

) comprising;

a) a destination circuit comprising at least one input; and

b) an interconnect circuit comprising a plurality of inputs and an output stage for routing a first signal from a selected input of the interconnect circuit to the input of said destination circuit, said output stage comprising a storage element for configurably storing said first signal from said selected input before supplying said first signal to the input of the destination circuit, wherein said storage element stores the first signal while the output stage supplies a second signal to the input of the destination circuit.

30. An integrated circuit (“

IC”

) comprising;

a) a destination circuit comprising at least one input; and

b) an interconnect circuit comprising a plurality of inputs and an output stage for routing a signal from a selected input of the interconnect circuit to the input of said destination circuit, said output stage comprising a storage element for configurably storing said signal from said selected input before supplying said signal to the input of the destination circuit, wherein said storage element receives the signal from the selected input and passes the signal to a particular input of the plurality of inputs after storing the signal.

31. An integrated circuit (“

IC”

) comprising;

a) a destination circuit comprising at least one input; and

b) an interconnect circuit comprising a plurality of inputs and an output stage for routing a signal from a selected input of the interconnect circuit to the input of said destination circuit, said output stage comprising a storage element for configurably storing said signal from said selected input before supplying said signal to the input of the destination circuit, wherein the output stage further comprises a feedback loop to an input of the plurality of inputs, wherein said storage element is located within the feedback loop.

32. The IC of claim 31, wherein the output stage further comprises an output that is directly connected to the input of the destination circuit.

33. An electronic device comprising:

a memory for storing configuration data; and

an integrated circuit (“

IC”

), said IC comprising;

a) a source circuit comprising at least one output;

b) a destination circuit comprising at least one input; and

c) a routing fabric comprising a plurality of wiring paths for passing signals between circuits of the IC, said routing fabric comprising a particular wiring path connecting the output of the source circuit to the input of the destination circuit,

wherein the particular wiring path comprises a first path and a second path that is parallel to said first path, said first path for configurably storing, based on a set of configuration data, a first output signal of the source circuit while said second path routes a second output signal of the source circuit to the destination circuit.

34. An electronic device comprising:

a memory for storing configuration data; and

an integrated circuit (“

IC”

), said IC comprising;

a) a destination circuit comprising at least one input;

b) an interconnect circuit comprising a plurality of inputs, an output stage for routing a signal from a selected input of the interconnect circuit to the input of said destination circuit, said output stage comprising a first storage element for configurably storing, based on a set of configuration data, said signal from said selected input before said signal is supplied to the input of the destination circuit; and

c) a second storage element for receiving said signal from the first storage element and storing said signal before supplying said signal to one of the inputs of the interconnect circuit.