Using programmable constant buffers for multi-threaded processing

• US 8,094,158 B1
• Filed: 01/31/2006
• Issued: 01/10/2012
• Est. Priority Date: 01/31/2006
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Allen, Roger L., Everitt, Cass W., Moreton, Henry P., Kong, Thomas H.
• Primary Examiner(s): Wang, Andrew
• Assistant Examiner(s): Merouan, Abderrahim
• Application Number:
  US11/344,306
• Time in Patent Office: 2,170 Days
• Field of Search: 718100-108, 345531-538, 711100-221
• US Class Current: 345/536
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 9/3832 Value prediction for operands; operand history buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.

Claims

1. A method of using multiple memory buffers for storing constant values utilized by shader programs during multi-threaded processing, comprising:

storing a first set of constant values in a first memory buffer;

loading a first entry corresponding to the first set of constant values in a constant buffer table with a base address of the first memory buffer, wherein each loaded entry in the constant buffer table is identifiable by an index value and comprises an address corresponding to one of the multiple memory buffers;

loading a first slot entry in a slot table with the index value associated with the loaded first entry in the constant buffer table, wherein each loaded slot entry in the slot table comprises an index value associated with one of the entries in the constant buffer table;

determining that a transition from configuration commands to data processing commands has occurred;

incrementing an inflight count indicating that the first set of constant values is a new version of the constant values; and

outputting an instruction associated with a first shader program to a data processing command path of a multiprocessor pipeline, wherein the instruction comprises an identifier for the first slot entry and an offset value and accesses a first value for a programmable constant in the first set of constant values that corresponds to the base address of the first memory buffer offset by the offset value.

2. The method of claim 1, further comprising updating an address translation table to associate the base address of the first memory buffer with the index value corresponding to the first entry in the constant buffer table.

3. The method of claim 1, further comprising:

storing a second set of constant values in a second memory buffer;

loading a second entry corresponding to the second set of constant values in the constant buffer table with a base address of the second memory buffer;

loading the first slot entry in the slot table with the index value associated with the second entry in the constant buffer table; and

executing an instruction associated with a second shader program while at least a portion of the first shader program is being executed, wherein the instruction associated with the second shader program comprises the identifier for the first slot entry and a second offset value and accesses a second programmable constant in the second set of constant values that corresponds to the base address of the second constant buffer offset by the second offset value.

4. The method of claim 1, further comprising:

storing a second set of constant values in a second memory buffer;

determining a reference count stored in the first entry in the constant buffer table indicating that the first slot entry in the slot table is bound to the first entry;

waiting for the first shader program to complete execution; and

loading the first entry in the constant buffer table with a base address of the second memory buffer; and

executing an instruction associated with a second shader program, wherein the instruction associated with the second shader program comprises the identifier for the first slot entry and a second offset value and accesses a second programmable constant in the second set of constant values that corresponds to the base address of the second constant buffer offset by the second offset value.

5. The method of claim 1, further comprising incrementing a reference count stored in the first entry in the constant buffer table to indicate that the first slot entry is bound to the first memory buffer.

6. The method of claim 1, further comprising:

unbinding the first slot entry in the slot table by clearing a bound flag stored in the first slot entry; and

decrementing a reference count stored in the first entry of the constant buffer table.

7. The method of claim 1, further comprising invalidating a cache entry that is accessed using the index value corresponding to the first entry in the constant buffer table.

8. The method of claim 1, wherein the slot table stores bindings to one or more of the multiple memory buffers for pixel shader programs, vertex shader programs, or geometry shader programs.

19. The method of claim 1, further comprising:

determining that a transition from the data processing commands to additional configuration commands has occurred;

generating a decrement inflight feedback command; and

outputting the decrement inflight feedback command to the data processing command path of the multiprocessor pipeline, wherein the inflight count is decremented after the decrement inflight feedback command is returned from the multiprocessor pipeline.

9. A system for storing multiple versions of multiple memory buffers for use during multi-threaded processing, comprising:

a multiprocessor pipeline configured to simultaneously execute data processing commands of a first shader program using a first set of constant values, wherein the first set of constant values is read using a first slot entry in slot table, wherein each filled slot entry in the slot table comprises a value corresponding to one of the multiple memory buffers;

a memory comprising a first memory buffer for storing the first set of constant values, wherein a first value for a programmable constant in the first set of constant values is stored in a first entry of the first memory buffer that corresponds to the base address of the first memory buffer offset by the offset value; and

a scalar processor array cache collector that is coupled between the memory and the multiprocessor pipeline and configured to determine when a transition from configuration commands to data processing commands has occurred and increment an inflight count indicating that the first set of constant values is a new version of the constant values when the transition from configuration commands to data processing commands has occurred.

10. The system of claim 9, further comprising a constant buffer table configured to store the base address of the first memory buffer in an entry of the constant table buffer to bind the first slot entry in the slot table to the first memory buffer or to store a base address of the second memory buffer in the entry to bind the first slot entry in the slot table to the second memory buffer, wherein the entry corresponds to an index that is stored in the first slot entry.

11. The system of claim 10, wherein the multiprocessor pipeline includes at least one address translation table configured to translate each index stored in the constant buffer table into a base address of a one of the memory buffers.

12. The system of claim 11, wherein the streaming processor array cache collector is further configured to generate and output a constant version update command including an index of an entry in the constant buffer table to the multiprocessor pipeline for updating the address translation table entry corresponding to the index.

13. The system of claim 12, wherein the streaming processor array cache collector includes a cache configured to store one or more constant values in the first set of constant values or in the second set of constant values used for the multi-threaded processing.

14. The system of claim 13, wherein the streaming processor array cache collector is configured to invalidate an entry in the cache corresponding to an index of the constant buffer table that has changed.

15. The system of claim 9, wherein the multiprocessor pipeline includes a cache configured to store one or more constant value in the first set of constant values or in the second set of constant values used for the multi-threaded processing.

16. The system of claim 9, wherein the streaming processor array cache collector includes a write buffer configured to accumulate one or more constant values in the first set of constant values to be stored in the first memory buffer or to accumulate one or more constant values in the second set of constant values to be stored in the second memory buffer.

17. The system of claim 9, wherein the slot table includes additional slot entries and is configured to bind the first slot entry and the additional slot entries to multiple buffers for use by only one type of shader program, wherein the type of shader program is one of a pixel shader program, a vertex shader program, and a geometry shader program.

18. The system of claim 17, further comprising a second slot table including slot entries and configured to bind the slot entries to memory buffers for use by a different type of shader program than the one type of shader program.

20. The system of claim 9, wherein the streaming processor array cache collector is further configured to:

determine when a transition from the data processing commands to additional configuration commands has occurred;

generate a decrement inflight feedback command; and

output the decrement inflight feedback command to the data processing command path of the multiprocessor pipeline, wherein the inflight count is decremented after the decrement inflight feedback command is returned from the multiprocessor pipeline.