Active device array substrate having bridge lines electrically connecting secondary and main data lines located on the same side of a pixel region and liquid crystal display panel and driving method thereof

• US 8,094,249 B2
• Filed: 09/19/2008
• Issued: 01/10/2012
• Est. Priority Date: 07/02/2008
• Status: Active Grant

• Current Assignee: Chunghwa Picture Tubes Limited
• Original Assignee: Chunghwa Picture Tubes Limited
• Inventors: Tsou, Yuan-Hsin, He, Chien-Kuo, Hung, Meng-Feng
• Primary Examiner(s): Le, Uyen Chau N
• Assistant Examiner(s): Mooney, Michael
• Application Number:
  US12/233,613
• Publication Number:
  US 20100002156A1
• Time in Patent Office: 1,208 Days
• Field of Search: 349/33, 349143-144, 349/38, 349/39, 349/139, 345/90, 345/92, 345 98-100, 345/103
• US Class Current: 349/33
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

An active device array substrate includes a number of scan lines, a number of data lines perpendicular to the scan lines, and a number of pixel regions. Each of the pixel regions includes a number of pixel sets arranged along a direction of the data lines. Each of the pixel sets has a number of adjacent pixels arranged along the direction of the data lines. The pixels in each of the pixel sets are electrically connected to the same data line. Each of the scan lines is separately arranged between the pixels. The data lines corresponding to the same pixel region are adjacent to one another and arranged at the same side of the pixel region.

Claims

1. An active device array substrate, comprising:

a plurality of scan lines;

a plurality of data lines perpendicular to the scan lines; and

a plurality of pixel regions, each of the pixel regions comprising a plurality of pixel sets arranged along a direction of the data lines, each of the pixel sets comprising a plurality of adjacent pixels arranged along the direction of the data lines, wherein the pixels in each of the pixel sets are electrically connected to the same data line, each of the scan lines is separately arranged between the pixels, and the data lines corresponding to the same pixel region are adjacent to one another and arranged at the same side of the same pixel region.

2. The active device array substrate as claimed in claim 1, wherein the pixel sets in each of the pixel regions comprise a first pixel set, a second pixel set, and a third pixel set, and the second pixel set is positioned between the first pixel set and the third pixel set.

3. The active device array substrate as claimed in claim 2, wherein the data lines corresponding to each of the pixel regions comprise a first data line, a second data line, and a third data line, and the first data line, the second data line, and the third data line are electrically connected to the first pixel set, the second pixel set, and the third pixel set, respectively.

4. The active device array substrate as claimed in claim 3, wherein the first data line corresponding to each of the pixel regions is disposed between the first pixel set and the second data line, and the second data line is disposed between the second pixel set and the third data line.

5. The active device array substrate as claimed in claim 1, wherein the data line corresponding to each of the pixel sets has a main line and a plurality of source connection lines, and the data line is electrically connected to the pixels through the source connection lines, respectively.

6. The active device array substrate as claimed in claim 5, wherein the length of the main lines is increased along with an increase in the minimum distance from the main lines to the corresponding pixels.

7. The active device array substrate as claimed in claim 5, wherein at least one of the data lines corresponding to each of the pixel regions further comprises a secondary line and a bridge line, the secondary line is parallel to the main line and is disposed between the main line and the corresponding pixel set, and through the bridge line the secondary line is connected to the main line in parallel.

8. The active device array substrate as claimed in claim 7, wherein the main line, the bridge line, the secondary line, and the source connection line are arranged along a signal transmitting direction of the data line.

9. The active device array substrate as claimed in claim 7, wherein the secondary line is disposed in an extending direction of the adjacent data lines.

10. The active device array substrate as claimed in claim 7, wherein the secondary line comprises a plurality of conductive line segments parallel to one another.

11. The active device array substrate as claimed in claim 7, wherein the bridge line comprises a plurality of conductive line segments parallel to one another.

12. The active device array substrate as claimed in claim 1, wherein each of the pixels comprises a pixel electrode and an active device, and the active device is electrically connected to the pixel electrode, the corresponding scan line, and the corresponding data line.

13. The active device array substrate as claimed in claim 12, wherein the pixel electrodes are not overlapped with the data lines.

14. The active device array substrate as claimed in claim 12, wherein each of the pixels further comprises a common electrode, and the common electrode and each of the pixel electrodes together form a storage capacitor.

15. The active device array substrate as claimed in claim 1, wherein the pixels in each of the pixel regions are substantially aligned to one another along the direction of the data lines.

16. A liquid crystal display panel, comprising:

an active device array substrate, comprising;

a plurality of scan lines;

a plurality of data lines perpendicular to the scan lines;

a plurality of pixel regions, each of the pixel regions comprising;

a first pixel set, comprising a plurality of first pixels electrically connected to the corresponding scan lines and a first data line among the data lines;

a second pixel set, comprising a plurality of second pixels electrically connected to the corresponding scan lines and a second data line among the data lines;

a third pixel set, comprising a plurality of third pixels electrically connected to the corresponding scan lines and a third data line among the data lines,

wherein the first pixels, the second pixels, and the third pixels in each of the pixel regions are arranged along a direction of the data lines, the first data line, the second data line, and the third data line corresponding to the same pixel region are adjacent to one another and disposed at the same side of the same pixel region, and the scan lines corresponding to each of the pixel regions are separately disposed among the first pixels, among the second pixels, and among the third pixels;

an opposite substrate; and

a liquid crystal layer, disposed between the active device array substrate and the opposite substrate, the first pixel sets corresponding to a first display region, the second pixel sets corresponding to a second display region, the third pixel sets corresponding to a third display region, wherein a brightness of the first pixels in an n^th row corresponding to the first display region, a brightness of the second pixels in the n^th row corresponding to the second display region, and a brightness of the third pixels in the n^th row corresponding to the third display region are simultaneously changed, and n is greater than or equal to 1.

17. The liquid crystal display panel as claimed in claim 16, wherein the length of each of the third data lines is greater than the length of each of the second data lines, and the length of each of the second data lines is greater than the length of each of the first data lines.

18. The liquid crystal display panel as claimed in claim 16, wherein each of the second data lines comprises:

a main line;

a secondary line, positioned in an extending direction of the first data line;

a bridge line, the secondary line being connected to the main line in parallel through the bridge line; and

a plurality of source connection lines, respectively connected to the corresponding second pixels, wherein the main line, the bridge line, the secondary line, and the source connection lines are arranged along a signal transmitting direction of the second data line.

19. The liquid crystal display panel as claimed in claim 16, wherein each of the third data lines comprises:

a main line;

a secondary line, positioned in an extending direction of the first data line and the second data line;

a bridge line, the secondary line being connected to the main line in parallel through the bridge line; and

a plurality of source connection lines, respectively connected to the corresponding third pixels, wherein the main line, the bridge line, the secondary line, and the source connection lines are arranged along a signal transmitting direction of the third data line.

20. The liquid crystal display panel as claimed in claim 16, wherein each of the first pixels, each of the second pixels, and each of the third pixels respectively comprise an active device and a pixel electrode.

21. The liquid crystal display panel as claimed in claim 20, wherein the pixel electrodes are not overlapped with the data lines.

22. The liquid crystal display panel as claimed in claim 20, wherein the first pixels, the second pixels, and the third pixels further comprise a common electrode, and the common electrode and each of the pixel electrodes together form a storage capacitor.

23. A method for driving the liquid crystal display panel as claimed in claim 16, the method comprising:

sequentially turning on the scan lines corresponding to the first pixel sets, sequentially turning on the scan lines corresponding to the second pixel sets, and sequentially turning on the scan lines corresponding to the third pixel sets, wherein a method of writing data signals into each of the first pixels, each of the second pixels, and each of the third pixels comprises;

simultaneously turning on first scan lines corresponding to the first pixel sets, the second pixel sets, and the third pixel sets, so as to simultaneously input a set of the data signals into the first pixel sets in a first row, the second pixel sets in a first row, and the third pixel sets in a first row through the first data lines, the second data lines, and the third data lines;

simultaneously turning off the first scan lines corresponding to the first pixel sets, the second pixel sets, and the third pixel sets;

simultaneously turning on next scan lines corresponding to the first pixel sets, the second pixel sets, and the third pixel sets, so as to simultaneously input another set of the data signals into the first pixel sets in a next row, the second pixel sets in a next row, and the third pixel sets in a next row through the first data lines, the second data lines, and the third data lines.