Semiconductor device

• US 8,094,480 B2
• Filed: 05/28/2009
• Issued: 01/10/2012
• Est. Priority Date: 05/30/2008
• Status: Expired due to Fees

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Tonomura, Yasuko
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US12/453,988
• Publication Number:
  US 20090296452A1
• Time in Patent Office: 957 Days
• Field of Search: 365/148, 365/163
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

A semiconductor device has a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements. The semiconductor device further has a reference system circuit enables measurement of distribution of the resistance values for the plurality of memory cells.

Claims

1. A semiconductor device comprising:

a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements; and

a reference system circuit enabling a measurement of distribution of the resistance values for the plurality of memory cells,

wherein the reference system circuit comprises a resistance selection circuit in which a resistance value of a reference resistance to be compared with the resistance values of the memory elements is variable from a first resistance value lower than a minimum resistance value that the memory elements assume up to a second resistance value higher than a maximum resistance value that the memory elements assume, and

wherein the resistance selection circuit comprises switches that are serially connected to a plurality of resistance elements having mutually different resistances via respective fuses to form serially-connected bodies, and these serially-connected bodies are connected in parallel, so that before disconnection of the fuses, the reference resistance is formed by selectively combining the plurality of resistance elements according to an externally input control signal, and after selective disconnection of the fuses, the reference resistance is formed by selectively combining the plurality of resistance elements according to the fuse state.

2. The semiconductor device of claim 1, further comprising:

a sense amplifier converting the resistance value of the memory element into a first potential;

a reference amplifier converting the resistance value of the reference resistance into a second potential; and

a comparator comparing the first potential with the second potential.

3. The semiconductor device of claim 2, further comprising

a plurality of the sense amplifiers and a plurality of the comparators, wherein the second potential is supplied in common to the comparators from the reference amplifier.

4. A reference level determination method comprising:

providing a semiconductor device comprising a reference system circuit including a plurality of reference resistances, and a resistance selection circuit connected to the plurality of reference resistances;

varying a resistance value of the reference system circuit to measure a distribution of resistance values of memory elements included in a plurality of memory cells of the semiconductor device; and

determining a resistance value of a reference resistance based on a degree of the distribution;

wherein when in the plurality of memory cells, there is a disparity between the degree of distribution in a low-resistance state and the degree of distribution in a high-resistance state, the resistance value of the reference resistance is determined to be a value biased to either one of the degrees of distribution having a higher distribution peak from the intermediate value between the resistance values in the low-resistance state and the resistance value in the high-resistance state.

5. The reference level determination method of claim 4, wherein the resistance value of the reference resistance is determined such that Rref=R1 max+(R0min−

R0max)·

hb/(ha+hb), where Rref is the reference resistance, R1 max is a maximum resistance of the distribution in the low-resistance state, R0min is a minimum resistance of the distribution in the high-resistance state, R0max is a maximum resistance of the distribution in the high-resistance state, and ha;

hb=H1;

H0, where H1 is a distribution peak height in the low-resistance state and H0 is a distribution peak height in the high-resistance state.

6. A semiconductor device comprising:

a plurality of memory cells including memory elements to store information by varying resistance values of the memory elements;

a reference system circuit including a variable resistance value to be output for a reference of the memory cells; and

first and second chips each of which includes the plurality of memory cells;

wherein the reference system circuit establishes, as the variable resistance value included therein, first and second resistance values, the first resistance value being established as a reference for the memory cells in the first chip, and the second resistance value being established as a reference for the memory cells in the second chip.

7. The semiconductor device of claim 6:

wherein each of the first and second chips includes a plurality of banks each of which includes the plurality of memory cells.