Non-volatile memory and method with write cache partitioning

• US 8,094,500 B2
• Filed: 01/05/2009
• Issued: 01/10/2012
• Est. Priority Date: 01/05/2009
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Paley, Alexander, Gorobets, Sergey Anatolievich, Zilberman, Eugene, Bennett, Alan David, Traister, Shai, Tomlin, Andrew, Wu, William S., So, Bum Suck
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US12/348,891
• Publication Number:
  US 20100172180A1
• Time in Patent Office: 1,100 Days
• Field of Search: 365/185.12, 365/185.11, 365/185.18
• US Class Current: 365/185.12
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5643 Multilevel memory comprising cache storage devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. Decisions to write data to the cache memory or directly to the main memory depend on the attributes and characteristics of the data to be written, the state of the blocks in the main memory portion and the state of the blocks in the cache portion.

Claims

1. A nonvolatile memory, comprising:

an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;

said array being partitioned into a first group of blocks and a second group of blocks;

a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel;

said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data;

said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; and

a controller for controlling writing data in a fragment of one or more partial page selectively either to the first group of blocks in granularity of a page or to the second group of blocks in granularity of one or more partial page, the selection to write to either first or second group being a function of predefined attributes of the data and predefined states of said first group of blocks and said second group of blocks.

2. The nonvolatile memory as in claim 1, wherein:

said predefined attributes of the data include a length of the fragment to be written.

3. The nonvolatile memory as in claim 1, wherein:

said fragment is from a host write; and

said predefined attributes of the data include a previous host write pattern.

4. The nonvolatile memory as in claim 1, wherein:

said predefined attributes of the data includes the fragment being a partial page.

5. The nonvolatile memory as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host; and

said predefined attributes of the data include a starting logical address of the fragment.

6. The nonvolatile memory as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host;

said first group of blocks stores data page by page preferably in sequential order of logical addresses; and

said predefined attributes of the data include a measure of how close a gap exists to appending sequentially the fragment to a partially empty block in the first group.

7. The nonvolatile memory as in claim 6, wherein:

the gap contains a range of logical addresses; and

and said predefined states of said first group of blocks and said second group of blocks include whether or not the data in the range of logical addresses exists in any one of the first group of blocks and the second group of blocks.

8. The method as in claim 6, wherein:

the gap contains a range of logical addresses; and

and said predefined states of said first group of blocks and said second group of blocks include whether or not the data in the range of logical addresses exists in any one of the first group of blocks and the second group of blocks.

9. The nonvolatile memory as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host;

said first group of blocks stores data page by page preferably in sequential order of logical addresses, each logical address in a block of the first group belonging to a predefined logical group of logical addresses; and

said predefined attributes of the data include whether the fragment contains logical addresses belonging to a logical group that coincides with that of a partially empty block in the first group.

10. The nonvolatile memory as in claim 1, wherein:

said predefined state of said first group of blocks includes whether or not the capacity of said first group of blocks has reached a predefined threshold.

11. The nonvolatile memory as in claim 1, wherein:

said predefined state of said second group of blocks includes whether or not the capacity of said second group of blocks has reached a predefined threshold.

12. The method as in claim 1, wherein:

said predefined attributes of the data include a length of the fragment to be written.

13. The method as in claim 1, wherein:

said fragment is from a host write; and

said predefined attributes of the data include a previous host write pattern.

14. The method as in claim 1, wherein:

said predefined attributes of the data includes the fragment being a partial page.

15. The method as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host; and

said predefined attributes of the data include a starting logical address of the fragment.

16. The method as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host;

said first group of blocks stores data page by page preferably in sequential order of logical addresses; and

said predefined attributes of the data include a measure of how close a gap exists to appending sequentially the fragment to a partially empty block in the first group.

17. The method as in claim 1, wherein:

the data is in logical units addressable by logical addresses assigned by a host;

said first group of blocks stores data page by page preferably in sequential order of logical addresses, each logical address in a block of the first group belonging to a predefined logical group of logical addresses; and

said predefined attributes of the data include whether the fragment contains logical addresses belonging to a logical group that coincides with that of a partially empty block in the first group.

18. The method as in claim 1, wherein:

said predefined state of said first group of blocks includes whether or not the capacity of said first group of blocks has reached a predefined threshold.

19. The method as in claim 1, wherein:

said predefined state of said second group of blocks includes whether or not the capacity of said second group of blocks has reached a predefined threshold.

20. In a nonvolatile memory having an array of memory cells organized into a plurality of blocks, each block being a plurality of memory cells that are erasable together;

a method of operating the nonvolatile memory, comprising;

partitioning the array into a first group of blocks and a second group of blocks;

providing a group of read/write circuits for reading or programming in the memory array a corresponding page of memory cells in parallel;

said first group of blocks having first-group pages that are each once programmable in between erasure, and the memory cells in the first-group page each storing one or more bit of data;

said second group of blocks having second-group pages that are each multi-time programmable with a partial page being once programmable each time, and the memory cells in the second-group page each storing one bit of data; and

writing data in a fragment of one or more partial page selectively either to the first group of blocks in granularity of a page or to the second group of blocks in granularity of one or more partial page, the selection to write to either first or second group being a function of predefined attributes of the data and predefined states of said first group of blocks and said second group of blocks.