Memory array incorporating noise detection line

• US 8,094,510 B2
• Filed: 07/30/2010
• Issued: 01/10/2012
• Est. Priority Date: 03/21/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E.
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US12/847,378
• Publication Number:
  US 20100290301A1
• Time in Patent Office: 529 Days
• Field of Search: 365/206, 365/51, 365/63
• US Class Current: 365/206
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2207/063 Current sense amplifiers
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/062 Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory cells, which substantially eliminates leakage current through half-selected memory cells. The bit line current which is sensed arises largely from only the current through the selected memory cell. A noise detection line in the memory array reduces the effect of coupling from unselected word lines to the selected bit line. In a preferred embodiment, a three-dimensional memory array having a plurality of rail-stacks forming bit lines on more than one layer, includes at least one noise detection line associated with each layer of bit lines. A sensing circuit is connected to a selected bit line and to its associated noise detection line.

Claims

1. An integrated circuit, comprising:

a multi-level memory array of memory cells having at least one layer of word lines and more than one layer of bit lines, each layer of bit lines includes a bit line group;

at least one noise detection line associated with each layer of bit lines;

a selection circuit that selects a selected bit line associated with a particular bit line group, and a selected noise detection line associated with said particular bit line group; and

a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line, said bit line sensing circuit includes a voltage sensing circuit;

said voltage sensing circuit includes a first precharge circuit for precharging said selected noise detection line to an unselected word line bias voltage; and

a second precharge circuit for precharging said selected bit line to a voltage other than the unselected word line bias voltage.

14. The integrated circuit according to claim 1, wherein said selected noise detection line is arranged so that memory cells coupled respectively thereto are substantially non-conductive.

15. The integrated circuit according to claim 1, wherein a second noise detection line is associated with said particular bit line group, said second noise detection line is arranged so that a subset of the memory cells coupled respectively thereto are substantially conductive.

16. The integrated circuit of claim 1, wherein memory cells coupled to each noise detection line remain unprogrammed.

17. The integrated circuit of claim 1, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to a particular selected noise detection line on the same bit line layer.

18. The integrated circuit of claim 1, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to another selected bit line on the same bit line layer at the same time.

19. The integrated circuit of claim 1, wherein alternating bit lines on a bit line layer form a first group and are associated with a selection circuit and sensing circuit disposed to one side of the array, and remaining bit lines on the layer form a second group and are associated with a selection circuit and sensing circuit disposed to a side of the array opposite the one side.

20. The integrated circuit of claim 1, wherein each respective bit line group on a bit line layer is associated with a respective noise detection line.

21. The integrated circuit of claim 1, wherein said multi-level memory array is arranged with a word line layer as the bottom-most layer of the memory array.

22. The integrated circuit of claim 1, wherein more than one noise detection line is associated with each selection circuit and sensing circuit.

2. An integrated circuit, comprising:

a multi-level memory array of memory cells having at least one layer of word lines and more than one layer of bit lines, each layer of bit lines includes a bit line group;

at least one noise detection line associated with each layer of bit lines;

a selection circuit that selects a selected bit line associated with a particular bit line group, and a selected noise detection line associated with said particular bit line group; and

a bit line sensing circuit, said bit line sensing circuit senses a signal on said selected bit line and a signal on said selected noise detection line;

wherein alternating bit lines on a bit line layer form a first group and are associated with a selection circuit and sensing circuit disposed to one side of the array, and remaining bit lines on the layer form a second group and are associated with a selection circuit and sensing circuit disposed to a side of the array opposite the one side.

3. The integrated circuit according to claim 2, wherein said selected noise detection line associated with said particular bit line group is arranged on the same layer of bit lines as said particular bit line group.

4. The integrated circuit according to claim 2, wherein said selected noise detection line is arranged so that memory cells coupled respectively thereto are substantially non-conductive.

5. The integrated circuit according to claim 2, wherein said bit line sensing circuit includes a voltage sensing circuit.

6. The integrated circuit according to claim 2, wherein a second noise detection line is associated with said particular bit line group, said second noise detection line is arranged so that a subset of the memory cells coupled respectively thereto are substantially conductive.

7. The integrated circuit of claim 2, wherein memory cells coupled to each noise detection line remain unprogrammed.

8. The integrated circuit of claim 2, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to a particular selected noise detection line on the same bit line layer.

9. The integrated circuit of claim 2, wherein said selection circuit is arranged so that a particular selected bit line on a bit line layer is never adjacent to another selected bit line on the same bit line layer at the same time.

10. The integrated circuit of claim 2, wherein each respective bit line group on a bit line layer is associated with a respective noise detection line.

11. The integrated circuit of claim 2, further comprising more than one selection circuit associated with each bit line group.

12. The integrated circuit of claim 2, wherein said multi-level memory array is arranged with a word line layer as the bottom-most layer of the memory array.

13. The integrated circuit of claim 2, wherein more than one noise detection line is associated with each selection circuit and sensing circuit.