Multi-bus structure for optimizing system performance of a serial buffer

• US 8,094,677 B2
• Filed: 02/27/2007
• Issued: 01/10/2012
• Est. Priority Date: 02/27/2007
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Chen, Ming-Shiung, Juan, Steve, Wang, Chi-Lie
• Primary Examiner(s): Moe, Aung S
• Assistant Examiner(s): Louis, Vincelas
• Application Number:
  US11/679,824
• Publication Number:
  US 20080205438A1
• Time in Patent Office: 1,778 Days
• Field of Search: 370/349, 370/412, 370/413, 370/417, 370/465, 370/229, 370/252, 370/395.42, 370/415, 370/394, 710/12, 710/27, 710/52, 710/107, 710/112, 710/305, 711/213, 709/232, 375/240.26
• US Class Current: 370/465
• CPC Class Codes: H04L 12/4015 by scheduling the transmission of messages at the communication node
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/2441 relying on flow classification, e.g. using integrated services [IntServ]

Abstract

A serial buffer having a parser and multiple parallel processing paths is provided. The parser receives incoming packets, determines the type of each packet, and then routes each packet to a processing path that corresponds with the determined packet type. Packet types may include blocking priority packets (which implement bus slave operations), non-blocking priority packets (which access on-chip resources of the serial buffer) and data packets (which implement bus master operations). Because the different packet types are processed on parallel processing paths, the processing of one packet type does not interfere with the processing of other packet types. As a result, blocking conditions within the serial buffer are minimized.

Claims

1. A serial buffer comprising:

a plurality of queues;

a plurality of configuration registers;

a parser coupled to receive incoming packets;

a first processing path coupled to receive packets of a first packet type from the parser, wherein the first processing path comprises slave read circuitry for performing slave read accesses on read ports of the plurality of queues in response to packets of the first packet type; and

a second processing path coupled to receive packets of a second packet type from the parser, wherein the second processing path comprises register access circuitry for accessing the configuration registers in response to packets of the second packet type;

a memory access engine that implements bus master read accesses on the read ports of the plurality of queues in response to fullness levels of the plurality of queues; and

egress control logic that routes data read from the configuration registers in response to packets of the second packet type with a higher priority than data read from the plurality of queues by the slave read accesses and the bus master read accesses.

2. The serial buffer of claim 1, wherein the first packet type has a first average processing time and the second packet type has a second average processing time, wherein the first average processing time is greater than the second average processing time.

3. The serial buffer of claim 1, further comprising:

a first input buffer configured to receive and store packets of the first packet type, which are provided to the first input buffer from the parser; and

a second input buffer configured to receive and store packets of the second packet type, which are provided to the second input buffer from the parser.

4. The serial buffer of claim 1, further comprising an output bus, wherein the egress control logic routes data read from the configuration registers and data read from the plurality of queues to the output bus, wherein the data read from the configuration registers is routed to the output bus without interference from the data read from the read ports of the plurality of queues.

5. The serial buffer of claim 1, wherein the plurality of configuration registers control operation of the serial buffer.

6. The serial buffer of claim 1, wherein some of the bus master read accesses block some of the slave read accesses, and vice versa.

7. The serial buffer of claim 1, wherein the first processing path operates in parallel with the second processing path, whereby the slave read accesses and the bus master read accesses do not interfere with the accesses to the configuration registers.

8. The serial buffer of claim 1, further comprising a third processing path coupled to receive packets of a third packet type from the parser, wherein the third processing path comprises write circuitry for performing write operations on write ports of the plurality of queues in response to packets of the third packet type.

9. The serial buffer of claim 8, wherein the write ports of the plurality of queues are separate from the read ports of the plurality of queues, whereby the write operations are performed in parallel with, and without interference from, the slave read accesses and the bus master read accesses.

10. The serial buffer of claim 8, wherein the first, second and third processing paths operate in parallel, whereby the slave read accesses and the bus master read accesses do not interfere with the accesses to the configuration registers or the write operations.

11. The serial buffer of claim 1, wherein a processing time associated with accessing the configuration registers is shorter than a processing time associated with performing the slave read accesses and the bus master read accesses.

12. A method of operating a serial buffer comprising:

receiving an incoming packet stream having a plurality of different packet types;

separating packets of the incoming packet stream based on the packet types;

processing packets of a first packet type in a first processing path of the serial buffer by performing slave read accesses on read ports of a plurality of queues of the serial buffer;

processing packets of a second packet type in a second processing path of the serial buffer by accessing configuration registers of the serial buffer;

initiating bus master read accesses on the read ports of the plurality of queues in response to fullness levels of the plurality of queues; and

routing data read from the configuration registers and data read from the plurality of queues to an outgoing bus, wherein the data read from the configuration registers is routed without interference from the data read from the plurality of queues.

13. The method of claim 12, further comprising processing packets of a third packet type in a third processing path of the serial buffer by performing write operations on write ports of the plurality of queues.

14. The method of claim 13, further comprising performing the write operations in parallel with, and without interference from, the slave read accesses and the bus master read accesses.

15. The method of claim 13, wherein the first, second and third processing paths operate in parallel, whereby the slave read accesses and the bus master read accesses do not interfere with the accesses to the configuration registers or the write operations.

16. The method of claim 12, further comprising controlling operations of the serial buffer in response to contents of the configuration registers.

17. The method of claim 12, wherein some of the bus master read accesses block some of the slave read accesses, and vice versa.

18. The method of claim 12, wherein the first processing path operates in parallel with the second processing path, and the slave read accesses and the bus master read accesses do not interfere with the accesses to the configuration registers.

19. The method of claim 12, wherein a processing time associated with accessing the configuration registers is shorter than a processing time associated with performing the slave read accesses and the bus master read accesses.