Method and apparatus for modeling source-drain current of thin film transistor

• US 8,095,343 B2
• Filed: 08/29/2008
• Issued: 01/10/2012
• Est. Priority Date: 12/17/2007
• Status: Expired due to Fees

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Shin, Jae Heon, Hwang, Chi Sun, Ryu, Min Ki, Cheong, Woo Seok, Chu, Hye Yong
• Primary Examiner(s): Shah, Kamini S
• Assistant Examiner(s): GEBRESILASSIE, KIBROM K
• Application Number:
  US12/201,457
• Publication Number:
  US 20090157372A1
• Time in Patent Office: 1,229 Days
• Field of Search: 703/2, 703/13, 703/14, 716/104, 716/136, 716/100, 716/106
• US Class Current: 703/2
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

Provided are a method and apparatus for modeling source-drain current of a TFT. The method includes receiving sample data, the sample data including a sample input value and a sample output value; adjusting modeling variables according to the sample data; calculating a current model value according to the adjusted modeling variables; when a difference between the calculated current model value and the sample output value is smaller than a predetermined threshold value, fitting a current model by applying the adjusted modeling variables to the current model; applying actual input data to the fitted current model; and outputting a result value corresponding to the actual input data, wherein the current model is a model for predicting the source-drain current of the TFT.

Claims

1. A method for modeling source-drain current of a thin film transistor (TFT), comprising:

(a) receiving experimentally determined sample data, the sample data including sample input values and a sample output value;

(b) adjusting modeling variables of a modeling equation according to the sample input values;

(c) calculating a model output value according to the adjusted modeling variables;

(d) repeating steps (b) and (c) with the adjusted modeling variables until a difference between the calculated model output value and the sample output value is smaller than a predetermined threshold value, the adjusted modeling variables when the difference becomes smaller than the threshold value being used as final modeling variables for the modeling equation;

applying values for V_G and V_D as actual input data to the modeling equation with the final modeling variables, where V_G is a gate voltage and V_D is a drain voltage; and

outputting a result value corresponding to the actual input data,

wherein the modeling equation predicts the source-drain current of the TFT,

wherein the modeling equation is I_DS=I_leak+(1/I_b+1/I_a)<sup>−

1</sup>, where I_DS denotes drain-source current, I_leak denotes leakage current of the TFT, I_b denotes a first current value that is a source-drain current value calculated in a regime below a threshold voltage, and Ia denotes a second current value that is a source-drain current value calculated in a regime above a threshold voltage,

wherein the first current value is determined by equations;

I_b=(WC/L)(K_b/(b+2))(V_GF^b+2−

(V_GF−

V_D)^b+2) when V_GF>

0, and

I_b=0 when V_GF≦

0

where V_GF denotes a difference between a gate voltage and a flat band voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, and K_b and b denote modeling variable values, and

wherein the second current value is determined by the following equation;

I_a=(WC/L)(K_a/(a+2))(V_GTe^a+2−

(V_GTe−

V_D)^a+2),

where V_GTe=(V_min/2)(1+(V_GT/V_min)+(Δ

²+(V_GT/V_min−

1)²)^0.5), V_GT denotes a difference between a gate voltage and a threshold voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, Vmin denotes a minimum voltage, ka and a denote modeling variable values, and Δ

denotes a variable indicating convergence strength.

2. The method of claim 1, wherein the TFT is one of an organic TFT, an oxide TFT and an amorphous silicon TFT.

3. The method of claim 1, wherein the sample input values are a drain voltage value and a gate voltage value, and the sample output value is a source-drain current value measured according to the sample input values.

4. An apparatus for modeling source-drain current of a TFT, comprising:

a sample-data input unit for receiving experimentally determined sample data, the sample data including sample input values and a sample output value;

a modeling equation fitting unit for iteratively determining final modeling parameters for use in a modeling equation, the modeling equation fitting unit including;

a variable adjusting unit for adjusting modeling variables of the modeling equation according to the sample input values;

a model calculating unit for iteratively calculating trial model output values according to the adjusted modeling variables;

an error calculating unit for calculating differences between the trial model output values and the sample output value;

an error determining unit for determining when one of the differences is smaller than a predetermined threshold value, and establishing the final modeling variables when the difference is smaller than the predetermined threshold value;

a model applying unit for applying the modeling variables established by the error determining unit to the modeling equation; and

a result-value output unit for applying values for V_G and V_D as actual input data to the modeling equation and outputting a result value corresponding to the actual input data, where V_G is a gate voltage and V_D is a drain voltage,

wherein the sample-data input unit, the modeling equation taking unit, the variable adjusting unit, the model calculating unit, the error calculating unit, the error determining unit, the model applying unit, and the result-value output unit are implemented in a computer,

wherein the modeling equation predicts the source-drain current of the TFT,

wherein the modeling equation is I_DS=I_leak+(1/I_b+1/I_a)<sup>−

1</sup>, where I_DS denotes drain-source current, I_leak denotes leakage current of the TFT, I_b denotes a first current value that is a source-drain current value calculated in a regime below a threshold voltage, and I_a denotes a second current value that is a source-drain current value calculated in a regime above a threshold voltage,

wherein the first current value is determined by the following equations;

I_b=(WC/L)(K_b/(b+2))(V_GF^b+2−

(V_GF−

V_D)^b+2) when V_GF>

0, and

I_b=0 when V_GF≦

0

where V_GF denotes a difference between a gate voltage and a flat band voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, and K_b and b denote modeling variable values, and

wherein the second current value is determined by the following equation;

I_a=(WC/L)(K_a/(a+2))(V_GTe^a+2−

(V_GTe−

V_D)^a+2),

where V_GTe=(V_min/2)(1+(V_GT/V_min)+(Δ

²+(V_GT/V_min−

1)²)^0.5). V_GTdenotes a difference between a gate voltage and a threshold voltage, W denotes a channel width, C denotes gate insulating capacitance, L denotes a channel length, V_D denotes a drain voltage, V_mindenotes a minimum voltage, K_a and a denote modeling variable values, and Δ

denotes a variable indicating convergence strength.

5. The apparatus of claim 4, wherein the first current value and the second current value are applied based on the threshold voltage.

6. The apparatus of claim 4, wherein the TFT is one of an organic TFT, an oxide TFT and an amorphous silicon TFT.

7. The apparatus of claim 4, wherein the sample input values are a drain voltage value and a gate voltage value, and the sample output value is a source-drain current value measured according to the sample input values.