Multi-node configuration of processor cards connected via processor fabrics

• US 8,095,691 B2
• Filed: 07/02/2010
• Issued: 01/10/2012
• Est. Priority Date: 06/14/2007
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Verdoorn, William Garrett Jr., Walls, Andrew Dale
• Primary Examiner(s): TSENG, CHENG YUAN
• Application Number:
  US12/830,275
• Publication Number:
  US 20100268986A1
• Time in Patent Office: 557 Days
• Field of Search: None
• US Class Current: 710/1
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B

Abstract

Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Claims

1. A system, comprising:

a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics;

a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics;

a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes; and

node management code executed by at least one processor card in each of the first and second nodes to perform operations, the operations comprising;

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor card to operate without the failed processor card in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node that does not include the failed processor card in response to the determining that the node does not include at least one operational processor card.

2. A system, comprising:

a first midplane including;

a first and second processor cards, wherein each processor card includes a processor fabric; and

a first communication interface connecting the first and second processor cards to enable communication between the first and second processor cards;

a second midplane including;

a third and fourth processor cards, wherein each processor card includes a processor fabric, wherein the first and third processor cards connect via their processor fabrics, and wherein the second and fourth processor cards connect via their processor fabrics; and

a second communication interface connecting the third and fourth processor cards to enable communication between the third and fourth processor cards; and

management code executed by at least one processor card to perform operations, the operations comprising;

detecting a failure of one processor card;

determining whether the failed processor card is connected via the processor fabrics to an operational processor card;

reconfiguring the failed and operational processor cards connected via their processor fabrics to operate without the failed processor card in response to the determining that the failed processor card is connected via the processor fabrics to the operational processor card; and

performing a failover to use processor cards connected via their processor fabrics that are not connected via processor fabrics to the failed processor card in response to the determining that the failed processor card is not connected via the processor fabrics to the operational processor card.

3. A method, comprising:

configuring a first node comprising a plurality of processor cards, each having a processor fabric, connected via their processor fabrics;

configuring a second node comprising a plurality of processor cards, each having a processor fabric, connected via their processor fabrics;

configuring a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes;

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor card to operate without the failed processor card in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node that does not include the failed processor card in response to the determining that the node does not include at least one operational processor card.

4. An article of manufacture comprising a computer readable storage including code executed in processor cards each having a processor fabric and coupled to one of a plurality of communication interfaces, wherein the code causes operations to be performed, the operations comprise:

configuring a first node comprising a plurality of the processor cards connected via their processor fabrics;

configuring a second node comprising a plurality of the processor cards connected via their processor fabrics;

configuring the communication interfaces, wherein each communication interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes;

detecting a failure of one processor card in one of the first or second node;

determining whether the node including the failed processor card includes at least one operational processor card;

reconfiguring the first or second node including the failed processor card to operate without the failed processor card in response to the determining that the node includes at least one operational processor card; and

performing a failover to use the first or second node that does not include the failed processor card in response to the determining that the node does not include at least one operational processor card.