Device for controlling access from a plurality of masters to shared memory composed of a plurality of banks each having a plurality of pages

• US 8,095,744 B2
• Filed: 11/07/2008
• Issued: 01/10/2012
• Est. Priority Date: 02/12/2008
• Status: Expired due to Fees

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kawamoto, Isao, Watanabe, Yoshiharu
• Primary Examiner(s): Ellis, Kevin
• Assistant Examiner(s): Namazi, Mehdi
• Application Number:
  US12/267,014
• Publication Number:
  US 20090204771A1
• Time in Patent Office: 1,159 Days
• Field of Search: 345/535, 710/40, 710/244, 710/309, 711/151, 711/158
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The memory access device includes: a plurality of command division sections provided for a plurality of masters; a plurality of inter-master arbitration sections provided for a plurality of banks; and a memory control section. Each of the command division sections divides a command issued by the corresponding master into a plurality of micro-commands when the access region of the command is over two or more banks among the plurality of banks, each of the micro-commands being a command accessing only one of the two or more banks, and gives each of the micro-commands to an inter-master arbitration section corresponding to the bank including the access region of the micro-command. Each of the inter-master arbitration sections arbitrates micro-commands given from the command division sections to select one. The memory control section selects one of a plurality of micro-commands selected by the inter-master arbitration sections to perform memory access.

Claims

1. A memory access device for controlling access of a plurality of masters to a shared memory, the shared memory having a plurality of banks, each of the plurality of banks having a plurality of pages, the device comprising:

a plurality of command division sections provided for the plurality of masters;

a plurality of inter-master arbitration sections provided for the plurality of banks; and

a memory control section,

wherein each of the plurality of command division sections divides a command issued by the corresponding master into a plurality of micro-commands when an access region of the command is over two or more banks among the plurality of banks, each of the plurality of micro-commands being a command accessing only one of the two or more banks, and sends each of the micro-commands to an inter-master arbitration section corresponding to the bank including an access region of the micro-command,

each of the plurality of inter-master arbitration sections arbitrates micro-commands given from the plurality of command division sections to select one of the micro-commands, and

the memory control section selects one of the plurality of micro-commands selected by the plurality of inter-master arbitration sections to perform memory access.

2. The device of claim 1, further comprising a priority assignment section for holding access priority information among the plurality of masters,

wherein the priority assignment section notifies all of the plurality of inter-master arbitration sections of the same priority information, and

each of the plurality of inter-master arbitration sections arbitrates the plurality of micro-commands according to the priority information.

3. The device of claim 1, further comprising a refresh generation section for issuing a refresh request command to the memory control section,

wherein the memory control section arbitrates the refresh request command and the micro-commands in arbitration of the plurality of micro-commands.

4. The device of claim 1, further comprising a plurality of master priority management sections provided for the plurality of masters,

wherein each of the plurality of inter-master arbitration sections selects a micro-command with reference to priority levels given from the plurality of master priority management sections in arbitration of the plurality of micro-commands.

5. The device of claim 4, further comprising:

a refresh generation section for issuing a refresh request command to the plurality of inter-master arbitration sections; and

a refresh priority management section,

wherein each of the plurality of inter-master arbitration sections arbitrates the plurality of micro-commands and the refresh request command with reference to priority levels given from the plurality of master priority management sections and a priority level given from the refresh priority management section in arbitration of the plurality of micro-commands.

6. The device of claim 4, wherein each of the plurality of inter-master arbitration sections notifies the memory control section of a priority level given from a master priority management section corresponding to a master issuing the selected micro-command, and

the memory control section refers to the priority level in arbitration of the plurality of micro-commands and selects a micro-command having a priority level higher than a predetermined level preferentially.

7. The device of claim 1, wherein the memory control section sends information on the access direction indicating whether the selected micro-command is read or write to the plurality of inter-master arbitration sections, and

each of the plurality of inter-master arbitration sections selects a micro-command having the same access direction as the information on the access direction preferentially.

8. The device of claim 1, wherein each of the plurality of command division sections holds a plurality of access commands, and issues a micro-command prepared from an accepted access command to an inter-master arbitration section corresponding to a bank unused by an access command accepted prior to the accepted access command or a bank for which a micro-command has already been accepted by the memory control section.

9. The device of claim 3, wherein the shared memory is individually refreshable by the unit of at least one bank, and

the refresh generation section issues a refresh request command by the individually refreshable bank unit.

10. The device of claim 5, wherein the memory is individually refreshable by the unit of at least one bank, and

the refresh generation section issues a refresh request command by the individually refreshable bank unit.

11. A system comprising:

a system LSI including a plurality of masters and the memory access device of claim 1; and

a memory composed of a plurality of banks, the memory being connected to the system LSI,

wherein the memory access device arbitrates access from the masters to the banks of the memory.