Memory block management

• US 8,095,765 B2
• Filed: 03/04/2009
• Issued: 01/10/2012
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Asnaashari, Mehdi, Chen, Alan, Nemazie, Siamack
• Primary Examiner(s): Gu, Shawn X
• Application Number:
  US12/397,396
• Publication Number:
  US 20100228940A1
• Time in Patent Office: 1,042 Days
• Field of Search: None
• US Class Current: 711/170
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7202 Allocation control and policies
• CPC Class Codes: G06F 2212/7209 Validity control, e.g. using flags, time stamps or sequence numbers
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Various embodiments include one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes. Embodiments include determining defective blocks within the planes. If none of the blocks at a particular block position are determined to be defective, embodiments include assigning the blocks at the particular block position to a super block, and if one or more of the blocks at a particular block position are determined to be defective, embodiments include: assigning the blocks at the particular block position determined to be defective to a super block; and assigning a respective replacement block to the super block for each of the one or more blocks at the particular block position determined to be defective. The respective replacement block is selected from a number of blocks within a respective one of the planes that includes the respective block determined to be defective.

Claims

1. A memory controller, comprising:

control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

determine defective physical blocks within the planes;

if none of the physical blocks at a particular block position are determined to be defective, assign the physical blocks at the particular block position to a super block; and

if one or more of the physical blocks at a particular block position are determined to be defective;

assign the physical blocks at the particular block position that were not determined to be defective to a super block; and

assign a respective replacement physical block to the super block for each of the one or more physical blocks at the particular block position that were determined to be defective;

wherein the respective replacement physical block is selected from a number of physical blocks within a respective one of the planes that includes a respective physical block that was determined to be defective.

2. The memory controller of claim 1, wherein:

at least one of the physical blocks at the particular block position that were determined to be defective is a grown defective physical block; and

the control circuitry is configured to dynamically assign a respective replacement physical block to a super block for each of the at least one physical blocks at the particular block position that were determined to be a grown defective physical block.

3. The memory controller of claim 1, wherein the control circuitry is configured to determine a number of physical blocks.

4. The memory controller of claim 3, wherein the number of physical blocks is determined based, at least partially, on an uppermost expected number of defective blocks per plane.

5. The memory controller of claim 3, wherein the number of physical blocks does not exceed an uppermost expected number of defective blocks per plane.

6. The memory controller of claim 1, wherein the control circuitry is configured to map a physical block determined to be defective to a replacement block at a different block position than the physical block determined to be defective.

7. The memory controller of claim 1, wherein the control circuitry is configured to treat an otherwise non-defective physical block as a defective block for each physical block within a particular same array and at the same particular block position as a physical block determined to be defective.

8. A memory controller, comprising:

control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

selectively assign at least some of the physical blocks to one of a super block of a first type and a super block of a second type;

wherein the first type of super block includes only physical blocks at a respective same block position across the at least two planes; and

wherein the second type of super block includes physical blocks, at a respective same block position across the at least two planes, that have not been determined to be defective, and at least one physical block, at a different block position, that replaces at least one physical block, at a particular block position, determined to be defective.

9. The memory controller of claim 8, wherein the control circuitry is configured to access a table that includes:

a number of entries each having mapping information corresponding to a respective super block of the first type; and

a number of entries each having an indication of a different table having mapping information corresponding to a respective super block of the second type.

10. The memory controller of claim 9, wherein the control circuitry is configured to, based on a particular logical super block address, search the different table to determine a physical super block address of a particular super block of the second type.

11. The memory controller of claim 10, wherein the different table includes a physical block address for each physical block assigned to the particular super block of the second type.

12. The memory controller of claim 10, wherein the memory unit includes multiple flash memory devices with each flash memory device including at least one memory array, and wherein the at least two planes are from at least two different memory arrays and are organized into one of a number of groups.

13. The memory controller of claim 8, wherein the block positions indicate physical locations of physical blocks within their respective planes.

14. A memory controller, comprising:

control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

selectively assign at least some of the physical blocks to one of a super block of a first type and a super block of a second type, each type of super block including no more than one physical block from a particular plane;

wherein the first type of super block includes only physical blocks at a particular block position across the at least two planes; and

determine if a physical block within the at least two planes of is defective; and

wherein a physical block at the block position of a physical block determined to be defective, and that has not been determined to be defective, is assigned to a super block of the second type.

15. The memory controller of claim 14, wherein the control circuitry is configured to prevent a block, at the block position of and in a same array as a block determined to be defective, that has not been determined to be defective, from being assigned to a super block of the second type.

16. The memory controller of claim 14, wherein one or more super blocks of the second type includes at least two blocks at a same block position.

17. The memory controller of claim 14, wherein one or more super blocks of the second type includes at least three blocks at a same block position.

18. The memory controller of claim 14, wherein the one or more memory devices form a portion of a flash solid state drive,

19. The memory controller of claim 14, wherein the physical blocks corresponding to a super block are substantially simultaneously erasable.

20. The memory controller of claim 14, wherein the first and second type of super blocks each include a same number of physical blocks.

21. A memory controller, comprising:

control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

determine if a physical block within the at least two planes is defective;

selectively assign at least some of the physical blocks to a respective one of the super blocks, wherein each of the super blocks has no more than one physical block from a particular plane; and

wherein at least one of the super blocks includes;

physical blocks at a particular block position across the at least two planes that have not been determined to be defective; and

a replacement block for a physical block, at the particular block position, that has been determined to be defective, the replacement physical block selected from an assigned group of physical blocks within a same plane as the physical block determined to be defective.

22. A method for block management in a memory system, the method comprising:

determining defective physical blocks within a memory unit having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes; and

assigning a physical block from each of the at least two planes to a respective one of the super blocks;

wherein each of the super blocks includes;

physical blocks, at a respective same block position of the at least two planes, that have not been determined to be defective; and

if a physical block at the respective same block position is determined to be defective, a replacement block for the physical block determined to be defective, the replacement physical block selected from physical blocks within a same plane as the physical block determined to be defective.

23. The method of claim 22, including assigning a number of physical blocks within each plane to be used to replace physical blocks that have been determined to be defective within each plane.

24. The method of claim 22, including mapping the physical block determined to be defective to the replacement block.

25. A method for block management in a memory system, the method comprising:

assigning physical blocks to a first type of super block associated with a memory unit, the memory unit having at least two different planes of physical blocks, with each super block including a physical block from each of the at least two different planes;

assigning physical blocks to a second type of super block associated with the memory unit;

wherein each super block of the first type includes only physical blocks at a respective block position across the at least two different planes; and

wherein each super block of the second type includes a physical block at a respective block position across the at least two different planes and a physical block at a different block position, the physical block at the different block position replacing a physical block, at the respective block position, that has been determined to be defective.

26. The method of claim 25, including preventing physical blocks at a same block position and in a same array as a block determined to be defective from being assigned to a super block of the second type.

27. The method of claim 25, including searching a table that includes:

a number of entries each having mapping information corresponding to a respective super block of the first type; and

a number of entries each having an indication of a different table having mapping information corresponding to a respective super block of the second type.

28. The method of claim 27, including searching the different table to determine a physical super block address of a particular super block of the second type based on a particular logical super block address.

29. A memory controller, comprising:

control circuitry coupled to one or more memory devices having at least two planes of physical blocks organized into super blocks, with each super block including a physical block from each of the at least two planes, and wherein the control circuitry is configured to;

determine defective physical blocks within the planes, the defective physical blocks including original defective blocks as well as grown defective blocks;

if none of a plurality of physical blocks at a particular block position are determined to be defective, assign the plurality of physical blocks at the particular block position to a super block; and

if one or more of the plurality of physical blocks at the particular block position number are determined to be defective;

assign the one or more physical blocks at the particular block position that were not determined to be defective to a super block; and

assign a respective replacement physical block to a super block for each of the one or more of the plurality of physical blocks at the particular block position that were determined to be defective;

wherein the respective replacement physical block is selected from an assigned number of physical blocks within a respective one of the planes that includes a respective physical block that was determined to be defective.

30. The memory controller of claim 29, wherein the control circuitry is configured to:

if one or more of the physical blocks currently assigned to a particular super block becomes a grown defective block,

assign a replacement block for the grown defective block from the assigned number of physical blocks within the respective one of the planes.