Method for address comparison and a device having address comparison capabilities

• US 8,095,769 B2
• Filed: 08/19/2008
• Issued: 01/10/2012
• Est. Priority Date: 08/19/2008
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Porat, Rotem, Anschel, Moshe, Peled, Itay, Steinberg, Erez, Zamsky, Ziv
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Ayash, Marwan
• Application Number:
  US12/194,273
• Publication Number:
  US 20100049939A1
• Time in Patent Office: 1,239 Days
• Field of Search: None
• US Class Current: 711/201
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 12/1441 for a range
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

Claims

1. A method for address comparison, the method comprising:

receiving an input address;

determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group;

wherein a comparison between the input address and a memory segment boundary comprises;

applying, by a comparison circuit, a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary;

ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and

comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary;

wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

2. The method according to claim 1 wherein the receiving is preceded by selecting a segment boundary to provide a highest boundary restriction in view of the size of the memory segment and in view of the alignment restriction.

3. The method according to claim 1 wherein the receiving of the input address is preceded by:

receiving an input memory segment boundary, an output memory segment boundary and a size of a input memory segment;

determining the alignment restriction in response to the input memory segment boundary and the output memory segment boundary; and

determining the location of bits that form the intermediate portion of the input address and of the memory segment boundary in response to the alignment restriction.

4. The method according to claim 1 comprising performing an address translation of the input address, if the input address is within the memory segment out of the group of memory segments.

5. The method according to claim 4 wherein the input address is an input address that belongs to an input memory segment out of the group of memory segments;

wherein the performing of the address translation comprises;

replacing bits of the most significant portion of the input address by corresponding bits of a most significant portion of an output memory segment base address;

copying the bits of the least significant portion of the input address; and

adding to the intermediate portion of the input address a difference between the output memory segment base address and an input memory segment base address.

6. The method according to claim 1 comprising determining whether the input address is within the memory segment out of the group of memory segments by comparing, in parallel, the input address to memory segment information of each memory segment of the group;

wherein at least two memory segments have different sizes.

7. The method according to claim 1 wherein the intermediate portion of the input address is less than one half of the input address.

8. The method according to claim 1 wherein the intermediate portion of the input address is less than one third of the input address.

9. The method according to claim 1 wherein the intermediate portion of the input address is smaller than the most significant portion of the input address.

10. The method according to claim 1 comprising selecting which bits of the input address to send to XOR logical gates, selecting which bits of the input address to send to the set of comparators and which bits of the input address to ignore.

11. A system having address comparison capabilities, the system comprising:

an interface for receiving an input address;

an address comparison unit, configured to determine whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment information of each memory segment of the group;

wherein the address comparison unit comprises multiple comparison modules;

each comparison module comprises a pair of comparison circuits;

whereas a first comparison circuit compares the input address to a memory segment boundary and a second comparison circuit compares the input address to a memory segment end address;

wherein the first comparison circuit comprises multiple XOR gates, a set of full comparators, and a selection circuit;

wherein the selection circuit is configured to;

provide bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary to the multiple XOR gates;

provide bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary to the set of comparators;

wherein the multiple XOR gates are configured to apply a XOR operation on the bits of the most significant portion of the input address and corresponding bits of the most significant portion of the memory segment boundary;

wherein the set of full comparators are configured to compare between the bits of the intermediate portion of the input address and the corresponding bits of the intermediate portion of the memory segment boundary;

wherein the address comparison unit ignores bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and

wherein the selection circuit is responsive to selection information that determined a location of bits that form the intermediate portion of the input address and of the memory segment boundary;

wherein the selection information is determined in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

12. The system according to claim 11 comprising a segment boundary determination unit that is configured to select a segment boundary to provide a highest boundary restriction in view of the size of the memory segment and in view of the alignment restriction.

13. The system according to claim 11 comprising a segment boundary determination unit that is configured to:

receive an input memory segment boundary, an output memory segment boundary and a size of an input memory segment;

determine the alignment restriction in response to the input memory segment boundary and the output memory segment boundary; and

determine the location of bits that form the intermediate portion of the input address and of the memory segment boundary in response to the alignment restriction.

14. The system according to claim 11 comprising an address translation unit that is configured to perform an address translation of the input address, if the input address is within the memory segment out of the group of memory segments.

15. The system according to claim 14 wherein the input address is an input address that belongs to an input memory segment out of a group of memory segments;

wherein the address translation unit performs an input to output address translation that comprises;

replacing bits of the most significant portion of the input address by corresponding bits of a most significant portion of an output memory segment base address;

copying the bits of the least significant portion of the input address; and

adding to the intermediate portion of the input address a difference between the output memory segment base address and an input memory segment base address.

16. The system according to claim 11 comprising at least two address comparison modules are associated with memory segments of different sizes.

17. The system according to claim 11 wherein the intermediate portion of the input address is less than one half of the input address.

18. The system according to claim 11 wherein the intermediate portion of the input address is less than one third of the input address.

19. The system according to claim 11 wherein the intermediate portion of the input address is smaller than the most significant portion of the input address.