Integrated circuit systems having processor-controlled clock signal generators therein that support efficient power management

• US 8,095,813 B2
• Filed: 12/30/2007
• Issued: 01/10/2012
• Est. Priority Date: 03/22/2004
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Pernia, Scott Michael, Cenger, Tunc Mahmut
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US11/967,236
• Publication Number:
  US 20080104435A1
• Time in Patent Office: 1,472 Days
• Field of Search: None
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: H03K 3/354 Astable circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary apparatus comprises a clock generator, a sensor, and a processor. The clock generator provides a clock signal on a first terminal which is couplable to the clock input terminal of the second circuitry. The sensor is coupled to a second terminal which is couplable to the inverted clock output terminal, and detects a power conservation mode and a power resumption mode of the second circuitry. The processor is adapted to reduce power to the clock generator and to provide a first predetermined voltage or a second predetermined voltage to the first and second terminals in response to the detection of the power conservation mode, and to increase power to the clock generator in response to the detection of the power resumption mode.

Claims

1. An integrated circuit system containing a clock generation apparatus coupled to second circuitry, the second circuitry having an input terminal and an output terminal, the clock generation apparatus comprising:

a clock generator adapted to provide a clock signal on a first terminal coupled to the input terminal;

a sensor coupled by a second terminal to the output terminal of the second circuitry, the sensor adapted to detect a power conservation mode and a power resumption mode of the second circuitry in response to a first signal and a second periodic signal generated by the second circuitry that identify the power conservation mode and the power resumption mode, respectively; and

a processor coupled to the sensor and to the clock generator, the processor configured to reduce power to the clock generator in response to detection of the power conservation mode by the sensor, and to increase power to the clock generator in response to detection of the power resumption mode by the sensor, said processor further configured to control the clock generator to convert the clock signal provided on the first terminal to a fixed voltage in response to detection of the power conservation mode by the sensor and convert the fixed voltage to the clock signal in response to detection of the power resumption mode by the sensor.

2. The integrated circuit system of claim 1, further comprising a memory coupled to the processor and adapted to store a power conservation mode parameter.

3. The integrated circuit system of claim 1, wherein the sensor comprises a voltage detector and an edge detector.

4. The integrated circuit system of claim 1, wherein the sensor comprises an edge detector.

5. The integrated circuit system of claim 4, wherein the sensor is adapted to detect commencement of the power resumption mode as a rising edge or as a falling edge of the second signal generated by the second circuitry and received at the second terminal.

6. The integrated circuit system of claim 1, wherein the sensor is adapted to detect the power conservation mode when the second signal received at the second terminal switches from being a periodic signal to a signal having a fixed voltage.

7. The integrated circuit system of claim 1, wherein the processor comprises a finite state machine.

8. The integrated circuit system of claim 1, wherein the processor comprises a finite state machine and combinational logic blocks.

9. The integrated circuit system of claim 1, wherein the clock generator comprises an oscillator, and wherein the processor is further adapted to power off the oscillator in response to the detection of the power conservation mode, and to power on the oscillator in response to the detection of the power resumption mode.

10. The integrated circuit system of claim 6, wherein the periodic signal is about 180 degrees out-of-phase relative to the clock signal generated at the first terminal by the clock generation apparatus and received at the input terminal of the second circuitry.

11. An integrated circuit system, comprising:

an integrated circuit configured to receive a clock signal at an input terminal thereof and generate a first fixed voltage signal at an output terminal thereof when said integrated circuit is disposed in a power conservation mode of operation, said integrated circuit further configured to convert the first fixed voltage signal generated at the output terminal into a periodic signal when said integrated circuit transitions from the power conservation mode of operation to a power resumption mode of operation; and

a clock generation apparatus having first and second terminals electrically coupled to the input and output terminals of said integrated circuit, respectively, said clock generation apparatus comprising;

a sensor configured to detect an edge transition of a signal received at the second terminal in response to said integrated circuit transitioning from the power conservation mode of operation to the power resumption mode of operation;

a clock generator configured to transition from generating a second fixed voltage signal to generating the clock signal at the first terminal, in response to said sensor detecting the edge transition of the signal received at the second terminal; and

a processor coupled to the sensor and to the clock generator, said processor configured to reduce power to said clock generator in response to detection of the power conservation mode by said sensor and further configured to increase power to said clock generator in response to detection by said sensor of the edge transition of the signal received at the second terminal.

12. The integrated circuit system of claim 11, wherein the periodic signal is about 180 degrees out-of-phase relative to the clock signal during power resumption mode of operation.

13. The integrated circuit system of claim 12, wherein the first fixed voltage signal and the second fixed voltage signal are generated at opposite logic levels by said integrated circuit and said clock generator, respectively.

14. The integrated circuit system of claim 13, wherein said sensor is configured to detect a low-to-high transition of a signal generated at the output terminal of said integrated circuit when said integrated circuit transitions from the power conservation mode of operation to the power resumption mode of operation.

15. The integrated circuit system of claim 11, wherein the first fixed voltage signal and the second fixed voltage signal are generated at opposite logic levels by said integrated circuit and said clock generator, respectively.

16. The integrated circuit system of claim 11, wherein said sensor is configured to detect a low-to-high transition of a signal generated at the output terminal of said integrated circuit when said integrated circuit transitions from the power conservation mode of operation to the power resumption mode of operation.