Error correction method with instruction level rollback

• US 8,095,825 B2
• Filed: 01/16/2007
• Issued: 01/10/2012
• Est. Priority Date: 01/16/2006
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Hirotsu, Teppei, Yamada, Hiromichi, Sakata, Teruaki, Hagiwara, Kesami
• Primary Examiner(s): Schell, Joseph
• Application Number:
  US11/623,441
• Publication Number:
  US 20070180317A1
• Time in Patent Office: 1,820 Days
• Field of Search: 714/17, 714/15, 714/16, 714/19, 714/21
• US Class Current: 714/17
• CPC Class Codes: G06F 11/1407 Checkpointing the instruction stream

Abstract

This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Claims

1. An error correction method, comprising:

detecting an error in a CPU bus write instruction in a CPU with a pipeline structure by a CPU bus error detector;

restoring, via a rollback control unit, a content of a register file from a delayed register file which holds the content of the register file at a time when an Instruction N was executed correctly before the error; and

re-executing, with rollback control, via a rollback control unit, an Instruction N+1 which is the next instruction after the Instruction N,

wherein the CPU and the rollback control unit are connected to one another via a bus,

wherein the CPU bus error detector decodes the CPU bus write instruction, and obtains an index of a register Ra which holds a write address of the CPU bus write instruction, and an index of a register Rd which holds write data of the CPU bus write instruction and compares the write address and write data outputted to the CPU bus with the value of Ra and Rd in the delayed register file, and

wherein instructions for setting the write address and write data to register Ra and register Rd are allocated so that the write address and write data are set to registers Ra and Rd in the delayed register file before the CPU bus write instruction is executed.

2. An error correction method for an information processing unit, which comprises a CPU with pipeline structure and a rollback control unit connected to the CPU via a bus, said method comprising:

when an error is detected, restoring a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error; and

re-executing an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N]

wherein;

the CPU includes a plurality of first flip flops, a parity check circuit and a second flip flop,

the rollback control unit include an error mask circuit,

the error mask circuit includes a plurality of mask logistics,

wherein output signals of the plurality of first flip flops are input to the parity check circuit, the parity check circuit inputs a signal obtained by collecting parity check results of each output signal by logical add to the second flip flop, and the second flip flop outputs an error detection signal, and

when the error detection signal is a predetermined value, the plurality of mask logics make an address, an instruction code, a write control and a write data into invalid values.

3. The error correction method according to claim 2,

wherein the [instruction N+1] is an instruction decoded first by the CPU among at least one or more instructions executed at the timing on which the error occurs.

4. The error correction method according to claim 2,

wherein a CPU signal inputted to the rollback control unit nullifies the CPU signal delayed by a latency portion of the error detection signal with the error detection signal, and

an output delay of the error detection signal is adjusted to be less than the minimum value of the output delay of the CPU signal.

5. An information processing unit for performing an error correction method, comprising:

a CPU with pipeline structure; and

a rollback control unit connected to the CPU via a bus which, when an error is detected, restores a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error and re-executes an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N],

wherein;

the CPU includes a plurality of first flip flops, a parity check circuit and a second flip flop,

the rollback control unit includes an error mask circuit,

the error mask circuit includes a plurality of mask logics,

output signals of the plurality of first flip flops are input to the parity check circuit, the parity check circuit inputs a signal obtained by collecting parity check results of each output signal by logical add to the second flip flop, and the second flip flop outputs an error detection signal, and

when the error detection signal is a predetermined value, the plurality of mask logics make an address, an instruction code, a write control and a write data into invalid values.

6. The information processing unit according to claim 5,

wherein the [instruction N+1] is an instruction decoded first by the CPU among at least one or more instructions executed at the timing on which the error occurs.

7. The information processing unit according to claim 5,

wherein a CPU signal inputted to the rollback control unit nullifies the CPU signal delayed by a latency portion of the error detection signal with the error detection signal, and

an output delay of the error detection signal is adjusted to be less than the minimum value of the output delay of the CPU signal.

8. An information processing unit for performing an error correction method, comprising:

a CPU with pipeline structure; and

a rollback control unit connected to the CPU via a bus, which, when an error is detected, restores a content of a register file from a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error and re-executes an instruction from an [Instruction N+1] which is the next instruction after the [Instruction N],

wherein;

the rollback control unit includes a CPU bus error detector which detects an error of a CPU bus write accompanied with execution of an instruction subsequent to the error occurrence,

the CPU bus error detector has a plurality of comparators, and

read data from the delayed register file and address data on the CPU bus are compared by the plurality of comparators and a bus write cancel is issued based on the comparison result.

9. The information processing unit according to claim 8,

wherein an instruction for generating a content of a source operand is disposed before the instruction accompanied with the CPU bus write so that the source operand of the instruction accompanied with the CPU bus write is reflected on the delayed register file before the CPU bus write, and

the error of the CPU bus write is detected by using the read value of the delayed register file and the CPU bus write related to the detected error is cancelled.