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Method and apparatus for testing semiconductor devices with autonomous expected value generation

  • US 8,095,841 B2
  • Filed: 08/19/2008
  • Issued: 01/10/2012
  • Est. Priority Date: 08/19/2008
  • Status: Expired due to Fees
First Claim
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1. Apparatus for interfacing a tester and a semiconductor device under test (DUT), comprising:

  • test probes configured to make temporary electrical contact with the DUT;

    connectors configured to connect to test channels from the tester;

    test resource extension circuitry configured to provide N number of test signals received through the connectors from the tester to K number of the test probes, wherein K is greater than N;

    output processing logic configured to receive from the test probes test result signals generated by the DUT in response to the test signals, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value;

    memory configured to store indications of whether each of the test result signals has the correct logic value.

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