Method and apparatus for testing semiconductor devices with autonomous expected value generation
First Claim
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1. Apparatus for interfacing a tester and a semiconductor device under test (DUT), comprising:
- test probes configured to make temporary electrical contact with the DUT;
connectors configured to connect to test channels from the tester;
test resource extension circuitry configured to provide N number of test signals received through the connectors from the tester to K number of the test probes, wherein K is greater than N;
output processing logic configured to receive from the test probes test result signals generated by the DUT in response to the test signals, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value;
memory configured to store indications of whether each of the test result signals has the correct logic value.
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Abstract
Method and apparatus for testing semiconductor devices with autonomous expected value generation is described. Examples of the invention can relate to apparatus for interfacing a tester and a semiconductor device under test (DUT). An apparatus can include output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; and memory configured to store indications of whether each of the test result signals has the correct logic value.
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Citations
30 Claims
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1. Apparatus for interfacing a tester and a semiconductor device under test (DUT), comprising:
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test probes configured to make temporary electrical contact with the DUT; connectors configured to connect to test channels from the tester; test resource extension circuitry configured to provide N number of test signals received through the connectors from the tester to K number of the test probes, wherein K is greater than N; output processing logic configured to receive from the test probes test result signals generated by the DUT in response to the test signals, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value;
memory configured to store indications of whether each of the test result signals has the correct logic value. - View Dependent Claims (2, 5, 6, 7, 8, 9)
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3. Apparatus for interfacing a tester and a semiconductor device under test (DUT), comprising:
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output processing logic configured to receive test result signals from the DUT responsive to testing by the tester, the output processing logic voting a logic value of a majority of the test result signals as a correct logic value; memory configured to store indications of whether each of the test result signals has the correct logic value; wherein the output processing logic includes voting logic configured to establish the correct logic value responsive to the test result signals and to compare each of the test result signals with the correct logic value to produce the indications; and
wherein the voting logic comprises;a first adder configured to produce a first sum of logic ‘
1’
values in the test result signals;a second adder configured to produce a second sum of logic ‘
0’
values in the test result signals; anda comparator configured to compare the first sum and the second sum and produce the correct logic value. - View Dependent Claims (4)
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10. A test system for testing a semiconductor device under test (DUT), comprising:
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test instruments having a tester; a probe card assembly having test probes configured to contact devices on the DUT; test resource extension circuitry configured to provide N number of test signals to K number of the test probes in contact with K number of pins of the DUT; output processing logic configured to receive test result signals from groups of pins of the DUT output by the DUT in response to the test signals, the output processing logic configured to vote a logic value of a majority of the test result signals for each group of the pins as a correct logic value; and memory configured to store indications of whether each of the test result signals for each group of the pins has the correct logic value. - View Dependent Claims (11, 12, 13, 14, 15, 18, 19, 29, 30)
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16. A test system for testing a semiconductor device under test (DUT), comprising:
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test instruments having a tester; a probe card assembly having test probes configured to contact devices on the DUT; output processing logic configured to receive test result signals from groups of pins of the DUT responsive to testing by the tester, the output processing logic configured to vote a logic value of a majority of the test result signals for each group of the pins as a correct logic value; memory configured to store indications of whether each of the test result signals for each group of the pins has the correct logic value; and circuits configured to interface the tester and the plurality of the devices on the DUT, each circuit interfacing with a respective one of the groups of pins, wherein the output processing logic includes voting logic disposed in each of the circuits, wherein the memory includes a memory circuit disposed in each of the circuits, and wherein the voting logic in each of the circuits comprises; a first adder configured to produce a first sum of logic ‘
1’
values in the test result signals on the group of pins interfacing such circuit;a second adder configured to produce a second sum of logic ‘
0’
values in the test result signals on the group of pins interfacing such circuit; anda comparator configured to compare the first sum and the second sum and produce the correct logic value. - View Dependent Claims (17)
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20. A method of testing a semiconductor device under test (DUT), comprising:
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providing N number of test signals to the DUT through K number of probes of a probe card assembly in contact with the DUT; capturing through the probes values of test result signals generated by the DUT in response to the test signals; voting a logic value of a majority of the test result signals as a correct logic value; comparing each of the values of the test result signals with the correct logic value; and storing indications of whether each of the test result signals has the correct logic value in a memory disposed on the probe card assembly. - View Dependent Claims (21, 22, 23)
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24. A probe card assembly, comprising:
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test probes configured to contact a semiconductor device under test (DUT); connectors configured to connect to test channels from a tester configured to test the DUT; test resource extension circuitry configured to provide N number of test signals received through the connectors from the tester to K number of the test probes, wherein K is greater than N; output processing logic configured to receive test result signals from groups of pins of the DUT generated by the DUT in response to the test signals, the output processing logic configured to vote a logic value of a majority of the test result signals for each group of the pins as a correct logic value; and memory configured to store indications of whether each of the test result signals for each group of the pins has the correct logic value. - View Dependent Claims (25, 26, 27, 28)
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Specification