Thin film transistors in pixel and driver portions characterized by surface roughness
First Claim
1. A thin film transistor comprising:
- a substrate including a pixel portion and a driver portion;
a first semiconductor layer disposed in the pixel portion and having a first surface roughness;
a second semiconductor layer disposed in the driver portion and having a second surface roughness larger than the first surface roughness, wherein the first semiconductor layer and the second semiconductor layer are disposed on the same substrate;
a first gate electrode disposed to correspond to the first semiconductor layer;
a second gate electrode disposed to correspond to the second semiconductor layer;
a gate insulating layer disposed between the first and second semiconductor layers and the first and second gate electrodes;
first source and drain electrodes electrically connected to source and drain regions of the first semiconductor layer; and
second source and drain electrodes electrically connected to source and drain regions of the second semiconductor layer, wherein,a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜
90%, andthe first surface roughness is 18-270 Å
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3 Assignments
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Accused Products
Abstract
A thin film transistor and a fabrication method thereof, in which one excimer laser annealing (ELA) makes a pixel portion and a driver portion different from each other in surface roughness and grain size. The thin film transistor includes: a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; a second semiconductor layer disposed in the driver portion and having a second surface roughness smaller than the first surface roughness; a gate insulating layer formed on the substrate including the first and second semiconductor layers; a first gate electrode placed to correspond to the first semiconductor layer on the gate insulating layer; a second gate electrode placed to correspond to the second semiconductor layer on the gate insulating layer; an interlayer insulating layer formed on the substrate including the first and second gate electrodes; first source and drain electrodes formed on the interlayer insulating layer and electrically connected with the first semiconductor layer; and second source and drain electrodes formed on the interlayer insulating layer and electrically connected with the second semiconductor layer.
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Citations
3 Claims
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1. A thin film transistor comprising:
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a substrate including a pixel portion and a driver portion; a first semiconductor layer disposed in the pixel portion and having a first surface roughness; a second semiconductor layer disposed in the driver portion and having a second surface roughness larger than the first surface roughness, wherein the first semiconductor layer and the second semiconductor layer are disposed on the same substrate; a first gate electrode disposed to correspond to the first semiconductor layer; a second gate electrode disposed to correspond to the second semiconductor layer; a gate insulating layer disposed between the first and second semiconductor layers and the first and second gate electrodes; first source and drain electrodes electrically connected to source and drain regions of the first semiconductor layer; and second source and drain electrodes electrically connected to source and drain regions of the second semiconductor layer, wherein, a root mean square (RMS) ratio of the first surface roughness to the second surface roughness is 25˜
90%, andthe first surface roughness is 18-270 Å
. - View Dependent Claims (2, 3)
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Specification
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- Resources
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Current AssigneeSamsung Display Company Limited (Samsung Electronics Co. Ltd.)
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Original AssigneeSamsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
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InventorsLee, Hong-Ro
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Primary Examiner(s)Gebremariam, Samuel
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Assistant Examiner(s)ARENA, ANDREW OWENS
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Application NumberUS11/954,716Publication NumberTime in Patent Office1,497 DaysField of Search257/72, 257/E29.003, 257/E21.413, 257/59, 257/66, 257/70, 257/E27.111, 257/E27.112, 257/E27.116, 257/E29.273, 257/E29.285, 257/E29.286, 257/E29.287, 257/E29.288, 257/E29.289, 257/E29.29, 257/E29.292, 257/E29.293, 257/E29.294, 257/E29.295, 257/E29.001, 257/E29.002, 257/E29.068, 257/E29.082, 257/E29.105, 257/E29.106, 257/E29.166, 257/E29.169, 257/E29.226, 257/E29.242, 257/E29.255US Class Current257/72CPC Class CodesH01L 27/12 the substrate being other t...H01L 27/1214 comprising a plurality of T...H01L 27/1285 using control of the anneal...H01L 29/04 characterised by their crys...
