Vertical transistors
First Claim
1. A transistor comprising:
- a semiconductor substrate;
a source region formed in a first pillar;
a drain region formed in a second pillar, the first and second pillars each having an inner wall, first and second outer sidewalls and an end wall, wherein the inner walls of the first and second pillars face each other, the end walls of the first and second pillars face away from each other, and the outer sidewalls connect the inner and end walls of each of the first and second pillars;
a dielectric material filling a region between the inner walls of the first and second pillars;
a first gate line facing the first outer sidewalls of the first and second pillars; and
a channel region gatedly connecting the source region in the first pillar to the drain region in the second pillar.
7 Assignments
0 Petitions
Accused Products
Abstract
The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.
-
Citations
14 Claims
-
1. A transistor comprising:
-
a semiconductor substrate; a source region formed in a first pillar; a drain region formed in a second pillar, the first and second pillars each having an inner wall, first and second outer sidewalls and an end wall, wherein the inner walls of the first and second pillars face each other, the end walls of the first and second pillars face away from each other, and the outer sidewalls connect the inner and end walls of each of the first and second pillars; a dielectric material filling a region between the inner walls of the first and second pillars; a first gate line facing the first outer sidewalls of the first and second pillars; and a channel region gatedly connecting the source region in the first pillar to the drain region in the second pillar. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A transistor array comprising:
-
a semiconductor substrate; a column of transistors, wherein two or more transistors in the column comprise a source region formed in a first pillar; a drain region formed in a second pillar, the first and second pillars each having an inner wall, first and second outer sidewalls and an end wall, wherein the inner walls of the first and second pillars face each other, the end walls of the first and second pillars face away from each other, and the outer sidewalls connect the inner and end walls of each of the first and second pillars; a dielectric material filling a region between the inner walls of the first and second pillars; a first gate line facing the first outer sidewalls of the first and second pillars; and a channel region gatedly connecting the source region in the first pillar to the drain region in the second pillar. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
-
Specification