Configurable inputs and outputs for memory stacking system and method

• US 8,098,508 B2
• Filed: 09/14/2009
• Issued: 01/17/2012
• Est. Priority Date: 12/30/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Round Rock Research LLC
• Inventors: Janzen, Jeffery W
• Primary Examiner(s): NGUYEN, VIET Q
• Application Number:
  US12/559,373
• Publication Number:
  US 20100002485A1
• Time in Patent Office: 855 Days
• Field of Search: 365/63, 257/686, 257/696, 438/109, 361/790
• US Class Current: 365/63
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/225 Clock input buffers
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/01055 Cesium [Cs]

Abstract

Embodiments of the present invention relate to configurable inputs and/or outputs for memory and memory stacking applications. More specifically, embodiments of the present invention include memory devices that include a die having a circuit configured for enablement by a particular signal, an input pin configured to receive the particular signal, and a path selector configured to selectively designate a signal path to the circuit from the input pin.

Claims

1. A memory device comprising:

a die including a top surface and a bottom surface separated by a thickness, the die configured to receive a control signal through a first path disposed through the die from the top surface to the bottom surface in a direction generally parallel to the thickness and through a second path disposed through the die from the top surface to the bottom surface in the direction generally parallel to the thickness;

a circuit included in the die, the circuit configured to be enabled by the control signal via the first path or the second path; and

a path selector configured to select the first path or the second path for transmission of the control signal.

2. The memory device of claim 1, comprising a first set of input pins enclosing the first path and a second set of input pins enclosing the second path.

3. The memory device of claim 2, wherein the first set of input pins and the second set of input pins comprise solder balls disposed on the top and bottom surfaces of the die.

4. The memory device of claim 1, wherein the path selector comprises a multiplexer.

5. The memory device of claim 1, wherein the control signal comprises a chip select signal, a clock enable signal, an on-die termination signal, or a calibration signal.

6. The memory device of claim 1, wherein the path selector includes a control circuit comprising a fuse.

7. A memory device comprising:

a die including a top surface and a bottom surface separated by a thickness, the die configured to receive a first control signal through a first path disposed through the die from the top surface to the bottom surface in a direction generally parallel to the thickness and to receive a second control signal through a second path disposed through the die from the top surface to the bottom surface in the direction generally parallel to the thickness;

a circuit included in the die, the circuit configured to be enabled by the first control signal via the first path or by the second control signal via the second path; and

a path selector configured to select the first path or the second path.

8. The memory device of claim 7, comprising a first set of input pins enclosing the first path and a second set of input pins enclosing the second path.

9. The memory device of claim 8, wherein the input pins comprise solder balls disposed on the top and bottom surfaces of the die.

10. The memory device of claim 8, wherein the first and second sets of input pins comprise chip select pins, wherein the first control signal comprises a chip select signal, and wherein the second control signal comprises a stacked chip select signal.

11. The memory device of claim 8, wherein the first and second sets of input pins comprise calibration input pins, wherein the first control signal comprises a calibration signal, and wherein the second control signal comprises a stacked calibration signal.

12. A memory device comprising:

a die including a top surface and a bottom surface separated by a thickness,

a first set of control input pins capable of receiving a first control signal and enclosing a first path disposed through the die from the top surface to the bottom surface in a direction generally parallel to the thickness;

a second set of control input pins capable of receiving a second control signal and enclosing a second path disposed through the die from the top surface to the bottom surface in the direction generally parallel to the thickness;

a circuit included in the die, the circuit configured to be enabled by the first control signal via the first path or by the second control signal via the second path; and

a path selector configured to select the first path or the second path.

13. The memory device of claim 12, wherein the control input pins comprise solder balls electrically coupled to the die.

14. The memory device of claim 12, wherein the first set of control input pins and the second set of control input pins comprise chip select pins, clock enable pins, on-die termination pins, or calibration input pins.

15. The memory device of claim 12, wherein the second control signal comprises a stacked version of the first control signal.

16. The memory device of claim 12, wherein the path selector comprises a selector control circuit comprising a fuse or antifuse and wherein the selector control circuit is configured to control the path selector.

17. The memory device of claim 12, wherein the circuit is disposed within the die between the first path and the second path.

18. The memory device of claim 12, comprising:

a third set of control input pins capable of receiving a third control signal and enclosing a third path disposed through the die from the top surface to the bottom surface in a direction generally parallel to the thickness;

a fourth set of control input pins capable of receiving a fourth control signal and enclosing a fourth path disposed through the die from the top surface to the bottom surface in a direction generally parallel to the thickness;

another circuit included in the die, the another circuit configured to be enabled by the third control signal via the third path or by the fourth control signal via the fourth path; and

another path selector configured to select the third path or the fourth path.

19. The memory device of claim 18, wherein the second control signal comprises a stacked version of the first control signal, and wherein the fourth control signal comprises a stacked version of the third control signal.

20. The memory device of claim 18, wherein the first and second sets of control input pins comprise chip select pins, wherein the first control signal comprises a chip select signal, wherein the second control signal comprises a stacked chip select signal, wherein the third and fourth sets of control input pins comprise calibration input pins, wherein the third control signal comprises a calibration signal, and wherein the fourth control signal comprises a stacked calibration signal.