Systems, methods and computer program products for high speed data transfer using a plurality of external clock signals

• US 8,098,784 B2
• Filed: 09/05/2006
• Issued: 01/17/2012
• Est. Priority Date: 09/05/2006
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E.
• Primary Examiner(s): Payne, David C.
• Assistant Examiner(s): Stevens, Brian J
• Application Number:
  US11/470,033
• Publication Number:
  US 20080059830A1
• Time in Patent Office: 1,960 Days
• Field of Search: 375/355, 375/354, 713/600
• US Class Current: 375/355
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

A method for capturing data includes receiving a plurality of external clock signals including a first external clock signal and a second external clock signal. Each external clock signal has a first frequency, a first edge and a second edge. Data is received on one or more signal links at a second frequency that is faster than the first frequency. The data includes consecutive data with a first data signal followed by a second consecutive data signal. The consecutive data is captured at the second frequency in response to the first edges and not the second edges of the external clock signals. The first data signal is captured based on the first edge of the first external clock signal and the second consecutive data signal is captured based on the first edge of the second external clock signal.

Claims

1. A method for capturing data, the method comprising:

receiving, at a device, a plurality of external clock signals including a first external clock signal and a second external clock signal, each of the external clock signals having the same first frequency, and each of the external clock signals having a first edge and a second edge, wherein a clock period of each of the external clock signals is the amount of time between any two successive first edges;

receiving, at the device, data on a signal link at a second frequency that is faster than the first frequency, the data including consecutive data comprising a first data signal followed by a second consecutive data signal; and

capturing the consecutive data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data signal is captured from the signal link using the first edge of the first external clock signal and the second consecutive data signal is captured from the signal link using the first edge of the second external clock signal.

2. The method of claim 1 further comprising transmitting a plurality of data signals on a second signal link, wherein the plurality of data signals is transmitted at a frequency faster than the first frequency.

3. The method of claim 2 wherein the second signal link is the signal link.

4. The method of claim 1 wherein the second frequency is equal to the number of external clock signals multiplied by the first frequency.

5. The method of claim 1 wherein each of the external clock signals consist of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

6. The method of claim 1 further comprising transforming the external clock signals into one or more internal clock signals and capturing the data in response to the internal clock signals, the internal clock signals at a higher frequency than the first frequency.

7. The method of claim 6 wherein the transforming includes applying a clock pulse shaper to the external clock signals.

8. The method of claim 1, wherein the device is a single memory device.

9. The method of claim 1, wherein the plurality of external clock signals consist of said first external clock signal and said second external clock signal.

10. A system for capturing data, the system comprising:

a plurality of external clock ports for receiving a plurality of external clock signals including a first external clock signal and a second external clock signal, each of the external clock signals having the same first frequency, and each of the external clock signals having a first edge and a second edge, wherein a clock period of each of the external clock signals is the amount of time between any two successive first edges;

a signal link port for receiving data at a second frequency faster than the first frequency, the data including consecutive data comprising a first data signal followed by a second consecutive data signal; and

logic in communication with the plurality of external clock ports and the signal link port for facilitating;

capturing the consecutive data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data signal received at the signal link port is captured using the first edge of the first external clock signal and the second consecutive data signal received at the signal link port is captured using the first edge of the second external clock signal.

11. The system of claim 10 wherein the second frequency is equal to the number of external clock signals times the first frequency.

12. The system of claim 10 wherein each of the external clock signals consist of any one of the first edge is a rising edge and the second edge is a falling edge, or the first edge is a falling edge and the second edge is a rising edge.

13. The system of claim 10 wherein the logic further facilitates transforming the external clock signals into one or more internal clock signals and capturing the data in response to the internal clock signals, the internal clock signals at a higher frequency than the first frequency.

14. The system of claim 13 wherein the transforming includes applying a clock pulse shaper to the external clock signals.

15. The system of claim 10, wherein the plurality of external clock ports, the signal link port, and the logic are located on a single memory device.

16. The system of claim 10, wherein the plurality of external clock signals consist of said first external clock signal and said second external clock signal.

17. A buffer device in a memory system, the buffer device comprising:

a plurality of external clock ports for receiving a plurality of external clock signals including a first external clock signal and a second external clock signal, each of the external clock signals having the same first frequency, and each of the external clock signals having a first edge and a second edge, wherein a clock period of each of the external clock signals is the amount of time between any two successive first edges;

a signal link port for receiving data at a second frequency faster than the first frequency, the data including consecutive data comprising a first data signal followed by a second consecutive data signal; and

logic in communication with the plurality of external clock ports and the one or more signal link ports for facilitating;

capturing the consecutive data at the second frequency in response to the first edges and not the second edges of the external clock signals, wherein the first data signal received at the signal link port is captured using the first edge of the first external clock signal and the second consecutive data signal received at the signal link port is captured using the first edge of the second external clock signal.

18. The buffer device of claim 17 wherein the buffer device is in communication with a memory controller via a memory bus and the consecutive data is received from the memory controller via the memory bus.

19. The buffer device of claim 17 wherein the buffer device is in communication with a memory device via a memory device interface.

20. The buffer device of claim 17, wherein the plurality of external clock ports, the signal link port, and the logic are located on a single memory controller.

21. The buffer device of claim 17, wherein the plurality of external clock signals consist of said first external clock signal and said second external clock signal.