CMOS transceiver analog front end having a combined power amplifier and low noise amplifier

• US 8,099,062 B1
• Filed: 04/24/2008
• Issued: 01/17/2012
• Est. Priority Date: 04/24/2008
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm Atheros Incorporated (Qualcomm, Inc.)
• Inventors: Terrovitis, Manolis
• Primary Examiner(s): West, Lewis
• Application Number:
  US12/109,268
• Time in Patent Office: 1,363 Days
• Field of Search: 455/73, 455/78, 455/83, 455/84
• US Class Current: 455/84
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A complementary metal oxide semiconductor transceiver analog front end circuit includes a combined transmit and receive amplifier block that produces an amplified transmit differential signal and receives a receive differential signal through the same pair of input/output nodes coupled to an external network through an RF choke block. In one embodiment the combined transmit and receive amplifier block includes separate power amplifier and low noise amplifier circuits, while a second embodiment includes a power amplification stage and a combined power amplification/low noise amplification stage. The amplifier circuits may be constructed using a combination of thin oxide core transistors and thick oxide input/output transistors. DC feeds may be selected to power the circuits in response to a transmit/receive control signal. Bias voltages to the amplifier circuits'"'"' transistors may also be set in response to the transmit/receive control signal.

Claims

1. A complementary metal oxide semiconductor (CMOS) transceiver analog front end circuit comprising:

a combined transmit and receive amplifier block including;

a transmit amplifier stage that receives a transmit differential signal at a first pair of nodes and produces a first stage amplified transmit differential signal at a third pair of nodes;

a shared transmit/receive amplifier stage that couples between the third pair of nodes and a second pair of nodes;

wherein, in transmit mode, the shared transmit/receive amplifier stage receives the first stage amplified transmit differential signal at the third pair of nodes and produces an amplified transmit differential signal at the second pair of nodes; and

,

wherein, in receive mode, the shared transmit/receive amplifier stage receives a receive differential signal at the second pair of nodes and produces an amplified receive differential signal at the third pair of nodes; and

a first bias voltage coupled to the shared transmit/receive amplifier stage;

an RF choke block coupled between the second pair of nodes and a pair of input/output nodes through which the amplified transmit differential signal and the receive differential signal couple to an antenna;

a selectable power feed, responsive to a transmit/receive control signal, coupled to the RF choke block;

a switched power feed, responsive to the transmit/receive control signal, coupled to the third pair of nodes.

2. The apparatus of claim 1 wherein,

in transmit mode, the selectable power feed, responsive to the transmit/receive control signal, couples a first voltage to the shared transmit/receive amplifier stage and the switched power feed, responsive to the transmit/receive control signal, decouples a second voltage from the shared transmit/receive amplifier stage;

and,

in receive mode, the switched power feed, responsive to the transmit/receive control signal, couples the second voltage to the shared transmit/receive amplifier stage and the selectable power feed, responsive to the transmit/receive control signal, couples a third voltage to the shared transmit/receive amplifier stage.

3. The apparatus of claim 2 wherein, in transmit mode, in response to the transmit/receive control signal, the first bias voltage is set to a first predetermined level, and in receive mode, in response to the transmit/receive control signal, the first bias voltage is set to a second predetermined level.

4. The apparatus of claim 3 wherein the shared transmit/receive amplifier stage comprises a first pair of transistors.

5. The apparatus of claim 4 wherein the transmit power amplifier stage comprises a second pair of transistors.

6. The apparatus of claim 5 wherein, in receive mode, the gates of the second pair of transistors is grounded.

7. The apparatus of claim 6 wherein the first pair of transistors are thick oxide input/output transistors and the second pair of transistors are thin oxide core transistors.

8. The apparatus of claim 4 wherein the transit amplifier stage comprises:

a first transmit amplification stage that receives the transmit differential signal and produces an intermediate stage amplified transmit differential signal,

a second transmit amplification stage that receives the intermediate stage amplified transmit differential signal and produces the first stage amplified transmit differential signal.

9. The apparatus of claim 8 further comprising:

a second bias voltage coupled to the second transmit amplification stage, wherein, the second bias voltage, in transmit mode, in response to the transmit/receive control signal, is set to a third predetermined level, and wherein, the second bias voltage, in receive mode, in response to the transmit/receive control signal, is grounded.

10. The apparatus of claim 9 wherein the first transmit amplification stage comprises a second pair of transistors and the second transmit amplification stage comprises a third pair of transistors.

11. The apparatus of claim 10 wherein the first pair of transistors are thick oxide input/output transistors, the second pair of transistors are thin oxide core transistors, and the third pair of transistors are thin oxide core transistors.

12. A CMOS transceiver analog front end circuit comprising:

a combined transmit and receive amplifier block that receives a transmit differential signal at a first pair of nodes and produces an amplified transmit differential signal at a second pair of nodes and that receives a receive differential signal at the second pair of nodes and produces an amplified receive differential signal at a third pair of nodes;

an RF choke block coupled between the second pair of nodes and a pair of input/output nodes through which the amplified transmit differential signal and the receive differential signal couple to an antenna;

a selectable power feed, responsive to a transmit/receive control signal, coupled to the RF choke block; and

,

a switched power feed, responsive to the transmit/receive control signal, coupled to the third pair of nodes.

13. The apparatus of claim 12 wherein the combined transmit and receive amplifier block comprises:

a first amplifier that receives the transmit differential signal at the first pair of nodes and produces the amplified transmit differential signal at the second pair of nodes;

a second amplifier that receives the receive differential signal at the second pair of nodes and produces the amplified receive differential signal at the third pair of nodes;

a first bias voltage coupled to the first amplifier; and

,

a second bias voltage coupled to the second amplifier;

wherein, in response to the transmit/receive control signal, in transmit mode, the first bias voltage is set to a first predetermined level and the second bias voltage is set to a second predetermined level; and

wherein, in receive mode, in response to the transmit/receive control signal, the first bias voltage is grounded and the second bias voltage is set to a third predetermined level.

14. The apparatus of claim 13 wherein, in transmit mode, the selectable power feed, responsive to the transmit/receive control signal, couples a first voltage to the first amplifier, and the switched power feed, responsive to the transmit/receive control signal, decouples a second voltage from the second amplifier;

and wherein, in receive mode, the selectable power feed, responsive to the transmit/receive control signal, couples a third voltage to the first amplifier, and the switched power feed, responsive to the transmit/receive control signal, couples the second voltage to the second amplifier.

15. The apparatus of claim 14 wherein the first amplifier comprises a first differential amplification stage that receives the transmit differential signal and produces a first stage amplified transmit differential signal;

and a second differential amplification stage that receives the first stage amplified transmit differential signal and produces the amplified transmit differential signal; and

the first bias voltage couples to the second differential amplification stage.

16. The apparatus of claim 15 wherein the first differential amplification stage comprises a first pair of transistors, the second differential amplification stage comprises a second pair of transistors, and the second amplifier comprises a third pair of transistors.

17. The apparatus of claim 16 wherein the first pair of transistors are thin oxide core transistors, the second pair of transistors are thick oxide input/output transistors and the third pair of transistors are thick oxide input/output transistors.

18. A CMOS transceiver analog front end circuit comprising:

a combined transmit and receive amplifier block that receives a transmit differential signal at a first pair of nodes and produces an amplified transmit differential signal at a second pair of nodes and that receives a receive differential signal at the second pair of nodes and produces an amplified receive differential signal at a third pair of nodes;

an RF choke block coupled between the second pair of nodes and a pair of input/output nodes through which the amplified transmit differential signal and the receive differential signal couple to an antenna; and

a power feed coupled to the RF choke block.

19. The apparatus of claim 18 wherein the combined transmit and receive amplifier block comprises:

a first amplifier that receives the transmit differential signal at the first pair of nodes and produces the amplified transmit differential signal at the second pair of nodes;

a second amplifier that receives the receive differential signal at the second pair of nodes and produces the amplified receive differential signal at the third pair of nodes;

a first bias voltage coupled to the first amplifier; and

,

a second bias voltage coupled to the second amplifier;

wherein, in response to a transmit/receive control signal, in transmit mode, the first bias voltage is set to a first predetermined level and the second bias voltage is set to a second predetermined level; and

wherein, in receive mode, in response to the transmit/receive control signal, the first bias voltage is grounded and the second bias voltage is set to a third predetermined level.

20. The apparatus of claim 19 wherein the first amplifier comprises a first differential amplification stage that receives the transmit differential signal and produces a first stage amplified transmit differential signal;

and a second differential amplification stage that receives the first stage amplified transmit differential signal and produces the amplified transmit differential signal; and

the first bias voltage couples to the second differential amplification stage.

21. The apparatus of claim 20 wherein the first differential amplification stage comprises a first pair of transistors, the second differential amplification stage comprises a second pair of transistors, and the second amplifier comprises a third pair of transistors.

22. The apparatus of claim 21 wherein the first pair of transistors are thin oxide core transistors, the second pair of transistors are thick oxide input/output transistors and the third pair of transistors are thick oxide input/output transistors.