Methods and devices for treating and processing data

• US 8,099,618 B2
• Filed: 10/23/2008
• Issued: 01/17/2012
• Est. Priority Date: 03/05/2001
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Maren Krass, Thomas Richter
• Inventors: Vorbach, Martin, Baumgarte, Volker
• Primary Examiner(s): Elamin, M
• Application Number:
  US12/257,075
• Publication Number:
  US 20090100286A1
• Time in Patent Office: 1,181 Days
• Field of Search: 713/300, 713/310, 713320-324, 713/330, 713/340, 713400-401, 713500-503, 713600-601
• US Class Current: 713/400
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3237 by disabling clock generation or distribution
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Claims

1. A Field Programmable Gate Array (FPGA), comprising:

a field of clocked configurable logic cells which is operable in different configurations; and

a clock preselecting arrangement configured to preselect logic cell clocking, wherein;

each of at least some of the configurable logic cells is dedicated to data processing and comprises a fixedly implemented arithmetic logic unit (ALU), operation of the ALU being configurable at runtime; and

the clock preselecting arrangement is adapted to, depending on the configuration, preselect a first clock at least at a first cell of the clocked logic cells and preselect an additional clock at least at an additional cell of the clocked logic cells.

2. The FPGA as recited in claim 1, wherein the clock preselecting arrangement is configured to receive a base clock for at least one cell from a unit preselecting configuration states.

3. The FPGA as recited in claim 1, wherein the clock preselecting arrangement is configured to receive a base clock from a logic cell.

4. The FPGA as recited in claim 1, wherein the clock preselecting arrangement includes at least one central clock preselecting unit and at least one local clock generating unit for generating a local clock from the preselected central clock.

5. The FPGA as recited in claim 1, wherein at least one of a memory and a register is assigned to at least a portion of the logic cells.

6. The FPGA as recited in claim 1, wherein the logic cells include a plurality of identical logic cells.

7. The FPGA as recited in claim 1, wherein all of the logic cells are identical.

8. The FPGA as recited in claim 1, wherein the preselection of the first clock at least at the first cell is for processing by the first cell according to the first clock and the preselection of the additional clock at least at the additional cell is for processing by the additional cell according to the additional clock simultaneously with the processing by the first cell.