Error detection in physical interfaces for point-to-point communications between integrated circuits

• US 8,099,648 B2
• Filed: 05/02/2011
• Issued: 01/17/2012
• Est. Priority Date: 03/09/2006
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Schmidt, Brian K., Butcher, Lawrence Llewelyn
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US13/099,254
• Publication Number:
  US 20110209027A1
• Time in Patent Office: 260 Days
• Field of Search: 714/758, 714/781, 714/799
• US Class Current: 714/758
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 2001/0092 Error control systems characterised by the topology of the transmission link
• CPC Class Codes: H04L 25/4908 using mBnB codes

Abstract

An apparatus, system and method for detecting errors in a physical interface during the transmission or receipt of data communications between integrated circuits (“ICs”) are disclosed. In one embodiment, a physical interface formed as a first IC on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface including multiple input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and one or more error recovery modules coupled between the plurality of input ports and output ports, where a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports.

Claims

1. A physical interface formed as a first integrated circuit (“

IC”

) on a first substrate portion to detect transmission errors in data exchanged with a second IC formed on a second substrate portion, the physical interface comprising;

a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and

one or more error recovery modules coupled between the plurality of input ports and output ports;

wherein a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports, the first error recovery module including a physical layer (“

PHY”

) decoder configured to detect errors in the in-bound encoded data bits and to initiate an action to correct the errors, the PHY decoder being an N+m bit/N bit decoder, where m is a integer of 1 or more.

2. The physical interface of claim 1, wherein the plurality of input ports and output ports includes a second subset of input ports configured to receive out-bound unencoded data bits from the second IC and a second subset of output ports configured to transmit out-bound encoded data bits, wherein a second error recovery module of the one or more error recovery modules is coupled between at least one of the second subset of input ports and at least one of the second subset of output ports, the second error recovery module including a PHY encoder configured to generate error-detection codes for the out-bound encoded data bits.

3. The physical interface of claim 2, wherein the PHY encoder is an N bit/N+m bit encoder, and the second IC is a core IC.

4. The physical interface of claim 2, wherein the second IC is a memory IC, and wherein the first subset of output ports are coupled to address bus inputs of the memory IC to communicate the in-bound decoded data bits as address bits and the second subset of input ports are coupled to data bus outputs of the memory IC to communicate the out-bound decoded data bits as memory data bits.

5. The physical interface of claim 4, wherein the first IC is a memory controller.

6. The physical interface of claim 1, wherein the first substrate further comprises an input-output (“

I/O”

) ring in which the physical interface is formed, wherein the first substrate portion and the second substrate portion are on the same substrate.

7. The physical interface of claim 6, wherein the first substrate portion and the second substrate portion are formed as a part of a system-on-chip (“

SOC”

).

8. An apparatus comprising:

a first substrate portion, the first substrate portion including a physical interface formed as a first integrated circuit (“

IC”

); and

a second substrate portion including a second IC, the first IC to detect transmission errors in data exchanged with the second IC;

wherein the physical interface comprises;

a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and

one or more error recovery modules coupled between the plurality of input ports and output ports;

wherein a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports, the first error recovery module including a physical layer (“

PHY”

) decoder configured to detect errors in the in-bound encoded data bits and to initiate an action to correct the errors, the PHY decoder being an N+m bit/N bit decoder, where m is a integer of 1 or more.

9. The apparatus of claim 8, wherein the plurality of input ports and output ports includes a second subset of input ports configured to receive out-bound unencoded data bits from the second IC and a second subset of output ports configured to transmit out-bound encoded data bits, wherein a second error recovery module of the one or more error recovery modules is coupled between at least one of the second subset of input ports and at least one of the second subset of output ports, the second error recovery module including a PHY encoder configured to generate error-detection codes for the out-bound encoded data bits.

10. The apparatus of claim 9, wherein the PHY encoder is an N bit/N+m bit encoder, and the second IC is a core IC.

11. The apparatus of claim 9, wherein the second IC is a memory IC, and wherein the first subset of output ports are coupled to address bus inputs of the memory IC to communicate the in-bound decoded data bits as address bits and the second subset of input ports are coupled to data bus outputs of the memory IC to communicate the out-bound decoded data bits as memory data bits.

12. The apparatus of claim 11, wherein the first IC comprises a memory controller.

13. The apparatus of claim 8, wherein the first substrate further comprises an input-output (“

I/O”

) ring in which the physical interface is formed, wherein the first substrate portion and the second substrate portion are on the same substrate.

14. The apparatus of claim 13, wherein the first substrate portion and the second substrate portion are formed as a part of a system-on-chip (“

SOC”

).

15. A system comprising:

a first element including a first substrate, the first substrate portion including a physical interface formed as a first integrated circuit (“

IC”

); and

a second element including a second substrate including a second IC, the first IC to detect transmission errors in data exchanged with the second IC;

wherein the physical interface comprises;

a plurality of input ports and output ports, including a first subset of input ports configured to receive in-bound encoded data bits and a first subset of output ports configured to transmit in-bound decoded data bits to the second IC; and

one or more error recovery modules coupled between the plurality of input ports and output ports;

wherein a first error recovery module of the one or more error recovery modules is coupled between at least one of the first subset of input ports and at least one of the first subset of output ports, the first error recovery module including a physical layer (“

PHY”

) decoder configured to detect errors in the in-bound encoded data bits and to initiate an action to correct the errors, the PHY decoder being an N+m bit/N bit decoder, where m is a integer of 1 or more.

16. The system of claim 15, wherein the plurality of input ports and output ports includes a second subset of input ports configured to receive out-bound unencoded data bits from the second IC and a second subset of output ports configured to transmit out-bound encoded data bits, wherein a second error recovery module of the one or more error recovery modules is coupled between at least one of the second subset of input ports and at least one of the second subset of output ports, the second error recovery module including a PHY encoder configured to generate error-detection codes for the out-bound encoded data bits.