L2 ECC implementation

• US 8,099,650 B1
• Filed: 08/29/2008
• Issued: 01/17/2012
• Est. Priority Date: 08/29/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Glasco, David B., Holmqvist, Peter B., Lynch, George R., Marchand, Patrick R., Mehra, Karan, Roberts, James
• Primary Examiner(s): Iqbal, Nadeem
• Application Number:
  US12/202,160
• Time in Patent Office: 1,236 Days
• Field of Search: 714751-755, 714757-764, 714766-769, 714/773, 714798-801
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories

Abstract

One embodiment of the present invention sets forth a method for implementing ECC protection in an on-chip L2 cache. When data is written to or read from an external memory, logic within the L2 cache is configured to generate ECC check bits and store the ECC check bits in the L2 cache in space typically allocated for storing byte enables. As a result, data stored in the L2 cache may be protected against bit errors without incurring the costs of providing additional storage or complex hardware for the ECC check bits.

Claims

1. A method for implementing error code correction (ECC) protection with respect to a write operation to an external memory via an intermediary cache, the method comprising:

receiving a write command that includes a word of data comprised of a plurality of bytes;

determining whether all bytes in the plurality of bytes are enabled or coherent;

once all bytes in the plurality of bytes are enabled or coherent, generating one or more ECC check bits for the plurality of bytes; and

storing the one or more ECC check bits in the intermediary cache instead of storing a byte enable for each byte in the plurality of bytes.

2. The method of claim 1, further comprising the step of setting an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of a byte enable for each byte in the plurality of bytes.

3. The method of claim 2, further comprising the step of storing the indicator bit in the intermediary cache.

4. The method of claim 1, wherein one or more bytes in the plurality of bytes are determined not to be enabled or coherent, and further comprising the steps of:

storing one or more bytes in the plurality of bytes that are enabled in the intermediary cache; and

issuing a read command to the external memory to obtain the one or more bytes in the plurality of bytes that are not enabled.

5. The method of claim 4, further comprising the steps of:

receiving from the external memory the one or more bytes that are not enabled;

merging the one or more bytes received from the external memory with the one or more bytes that are enabled and stored in the intermediary cache; and

storing the merged bytes in the intermediary cache.

6. The method of claim 1, wherein one or more bytes in the plurality of bytes are determined to be coherent but not enabled, and further comprising the steps of:

merging the one or more bytes determined to be coherent but not enabled with the one or more bytes that are enabled and stored in the intermediary cache; and

storing the merged bytes in the intermediary cache.

7. The method of claim 1, wherein the one or more ECC check bits are stored within a byte enable storage element within the intermediary cache, and further comprising the step of storing the plurality of bytes in a data storage element within the intermediary cache.

8. A computer-readable storage medium including instructions that, when executed by a processor, causes the processor to implement error code correction (ECC) protection with respect to a write operation to an external memory via an intermediary cache, by performing the steps of:

receiving a write command that includes a word of data comprised of a plurality of bytes;

determining whether all bytes in the plurality of bytes are enabled or coherent;

once all bytes in the plurality of bytes are enabled or coherent, generating one or more ECC check bits for the plurality of bytes; and

storing the one or more ECC check bits in the intermediary cache instead of storing a byte enable for each byte in the plurality of bytes.

9. The computer-readable storage medium of claim 8, further comprising the step of setting an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of a byte enable for each byte in the plurality of bytes.

10. The computer-readable storage medium of claim 9, further comprising the step of storing the indicator bit in the intermediary cache.

11. The computer-readable storage medium of claim 8, wherein one or more bytes in the plurality of bytes are determined not to be enabled or coherent, and further comprising the steps of:

storing one or more bytes in the plurality of bytes that are enabled in the intermediary cache; and

issuing a read command to the external memory to obtain the one or more bytes in the plurality of bytes that are not enabled.

12. The computer-readable storage medium of claim 11, further comprising the steps of:

receiving from the external memory the one or bytes that are not enabled;

merging the one or more bytes received from the external memory with the one or more bytes that are enabled and stored in the intermediary cache; and

storing the merged bytes in the intermediary cache.

13. The computer-readable storage medium of claim 8, wherein one or more bytes in the plurality of bytes are determined to be coherent but not enabled, and further comprising the steps of:

merging the one or more bytes determined to be coherent but not enabled with the one or more bytes that are enabled and stored in the intermediary cache; and

storing the merged bytes in the intermediary cache.

14. The computer-readable storage medium of claim 8, wherein the one or more ECC check bits are stored within a byte enable storage element within the intermediary cache, and further comprising the step of storing the plurality of bytes in a data storage element within the intermediary cache.

15. A computer system configured to implement error code correction (ECC) protection with respect to a write operation to an external memory via an intermediary cache comprising:

a central processing unit (CPU);

system memory coupled to the CPU; and

a parallel processing subsystem coupled to the CPU and to the external memory and including the intermediary cache, wherein the intermediary cache includes;

a data storage element

a byte enable storage element, and

control logic configured to;

receive a write command that includes a word of data comprised of a plurality of bytes,

determine whether all bytes in the plurality of bytes are enabled or coherent,

once all bytes in the plurality of bytes are enabled or coherent, generate one or more ECC check bits for the plurality of bytes,

store the plurality of bytes in the data storage element, and

store the one or more ECC check bits in the byte enable storage element instead of storing a byte enable for each byte in the plurality of bytes.

16. The computer system of claim 15, wherein the control logic is further configured to set an indicator bit indicating that the intermediary cache includes the one or more ECC check bits instead of a byte enable for each byte in the plurality of bytes.

17. The computer system of claim 16, wherein the intermediary cache further comprises an indicator storage element, and the control logic is further configured to store the indicator bit in the indicator storage element.

18. The computer system of claim 15, wherein the control logic determines that one or more bytes in the plurality of bytes are not enabled or coherent, and the control logic is further configured to:

store one or more bytes in the plurality of bytes that are enabled in the data storage element;

issue a read command to the external memory to obtain the one or more bytes in the plurality of bytes that are not enabled;

receive from the external memory the one or bytes that are not enabled;

merge the one or more bytes received from the external memory with the one or more bytes that are enabled and stored in the data storage element; and

store the merged bytes in the data storage element.

19. The computer system of claim 15, wherein the control logic determines that one or more bytes in the plurality of bytes are coherent but not enabled, and the control logic is further configured to:

merge the one or more bytes determined to be coherent but not enabled with the one or more bytes that are enabled and stored in the intermediary cache; and

store the merged bytes in the intermediary cache.

20. The computer system of claim 15, wherein the parallel processing subsystem comprises a graphics subsystem that includes a graphics processing unit.