Automatic integrated circuit routing using spines

• US 8,099,700 B1
• Filed: 08/14/2007
• Issued: 01/17/2012
• Est. Priority Date: 06/07/2004
• Status: Active Grant

• Current Assignee: Pulsic Limited
• Original Assignee: Pulsic Limited
• Inventors: Waller, Mark, Parker, Tim, Williams, Mark, Birch, Jeremy, Balsdon, Graham, Sato, Fumiako
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US11/838,726
• Time in Patent Office: 1,617 Days
• Field of Search: 716/1, 716/12, 716/13, 716/15, 716/126
• US Class Current: 716/126
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

A method and technique of routing interconnects of an integrated circuit providing improved routing quality. In an embodiment of the invention, the technique provides linear spine interconnect routing. In memory array blocks, such as in DRAM and SRAM memory designs, connected pins are generally separated by large distances in a first direction and small distances in a second direction, or a spine or channel region. A route area is defined within the spine region. In one embodiment, obstacles in the route area are identified and corresponding forbidden areas are demarcated. The linear spine interconnect is routed in the first direction within the route area while avoiding the forbidden areas. Pins are connected to the spine interconnect by stitching interconnects. Stitching interconnects are generally routed in the second direction.

Claims

1. A method for routing at least one interconnect of an integrated circuit comprising:

identifying at least two pins to couple;

by using a computer, calculating a route area having a boundary so that the at least two pins touch the boundary, wherein the route area has a rectangular shape and is bounded by a first, second, third, and fourth side, the third side is opposite of the first side, the fourth side is opposite of the second side, the first side is longer than the second side, the first and third sides extend in a first direction, the second and fourth sides extend in a second direction, and the second direction is orthogonal to the first direction;

routing a spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction; and

routing a plurality of stitching interconnects in the second direction to couple the first pin and second pin to the spine interconnect.

2. The method of claim 1 wherein the route area in the second direction extends between the most oppositely disposed in the second direction of the at least two pins.

3. The method of claim 1 further comprising determining a position in the second direction for the spine interconnect to reduce an average length of the plurality of stitching interconnects.

4. The method of claim 3 wherein the position of the spine interconnect in the second direction is a weighted average of positions in the second direction of the at least two pins.

5. The method of claim 1 further comprising:

determining if at least one forbidden area is located within the route area, the at least one forbidden area extends in the first direction the entire length of the route area in the first direction and comprises at least one obstacle,

wherein routing the spine interconnect excludes the at least one forbidden area.

6. The method of claim 5 wherein the position of the spine interconnect in the second direction is a closest available position outside the at least one forbidden area to a weighted average of positions in the second direction of the at least two pins positions.

7. The method of claim 5 further comprising determining if a path of each of the plurality of stitching interconnects is unobstructed by the at least one obstacle.

8. The method of claim 1 wherein an edge of the route area being an edge of a chip, the edge of the chip includes one of the at least one pins.

9. The method of claim 1 further comprising automatically routing at least one shield parallel to the spine interconnect.

10. The method of claim 9 wherein the at least one shield comprises two shields disposed on opposite sides of the spine interconnect.

11. The method of claim 9 wherein the at least one shield is coupled to a ground potential.

21. The method of claim 1 wherein the at least two pins touch at least the first or third sides.

22. The method of claim 1 wherein the routing a spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction is replaced by

routing a spine interconnect extending in the first direction at least a length of the first side in the first direction.

23. The method of claim 1 wherein the route area comprises the spine interconnect and the plurality of stitching interconnects.

12. A method for routing a plurality of nets of an integrated circuit comprising:

identifying pins to couple for each net;

by using a computer, calculating a route area for each net to comprise positions in a first direction of the pins for such net, wherein a boundary of the route area comprises at least a first side and a second side, the first side is opposite of the second side, and each of the pins touches the first or second side;

determining for each route area if at least one forbidden area is located within the route area;

routing outside of the at least one forbidden area a plurality of spine interconnects extending in a first direction the entire length of each corresponding route area in the first direction; and

routing a plurality of stitching interconnects in a second direction to couple each of the pins to the corresponding spine interconnect,

wherein the at least one forbidden area being an area to include at least one obstacle and extending in the first direction an entire length of the corresponding route area in the first direction.

13. The method of claim 12 further comprising automatically routing the plurality of spine interconnects to be spaced to satisfy a design constraint.

14. The method of claim 13 wherein the design constraint comprises at least one of spacing, crosstalk, capacitance, or timing.

15. The method of claim 12 further comprising automatically routing a first interconnect to match a timing delay of a second interconnect by lengthening the first interconnect.

16. The method of claim 12 further comprising automatically routing a first interconnect to match a timing delay of a second interconnect by increasing the spacing between the first interconnect and a third interconnect.

24. The method of claim 12 wherein the route area has a trapezoid shape.

25. The method of claim 12 wherein the route area has a rectangle shape.

26. The method of claim 12 wherein a length of the spine interconnects have a length at least equal to a length of the first side.

27. The method of claim 12 wherein the route area comprises the spine interconnect and the plurality of stitching interconnects.

17. A method of routing at least one interconnect of an integrated circuit comprising:

by using a computer, identifying at least two pins to couple, wherein each pin has a position in a first direction and a position in a second direction, orthogonal to the first direction;

calculating a route area having a boundary, the route area extending a distance in the first direction to comprise positions in the first direction of the at least two pins, wherein the at least two pins are on the boundary of the route area;

determining if at least one forbidden area is located within the route area, wherein the at least one forbidden area extends in the first direction the entire length of the route area in the first direction and comprises at least one obstacle;

routing a spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction, wherein the spine interconnect is placed outside of the at least one forbidden area; and

routing a plurality of stitching interconnects in the second direction to couple the first pin and second pin to the spine interconnect,

wherein a position in the second direction of the spine interconnect is at an available position, outside the at least one forbidden area, based on a function of the at least two pins.

18. The method of claim 17 wherein the function comprises a quotient of a sum of positions of the pins in the second direction and a total number of the at least two pins.

19. The method of claim 17 wherein the function comprises a weighted average of positions in the second direction of the at least two pins.

20. The method of claim 17 wherein the available position is at a position not occupied by another spine interconnect.

28. The method of claim 17 wherein the boundary of the route area comprises a first in the first direction, second in the second direction, third in the first direction, and fourth side in the second direction, the third side is opposite of the first side, the fourth side is opposite of the second side, and the first side is longer than the second side.

29. The method of claim 28 wherein the at least two pins are on at least the first side or the third side.

30. The method of claim 28 wherein the entire length of the route area is equal to a length of the first side.

31. The method of claim 17 wherein the routing a spine interconnect extending in the first direction at least a length from a first pin to a second pin in the first direction, wherein the spine interconnect is placed outside of the at least one forbidden area is replaced by

routing a spine interconnect extending in the first direction at least the entire length of the route area, wherein the spine interconnect is placed outside of the at least one forbidden area.

32. The method of claim 17 wherein the route area comprises the spine interconnect and stitching interconnects.