Field configured electronic circuits and methods of making the same

• US 8,099,707 B1
• Filed: 03/17/2009
• Issued: 01/17/2012
• Est. Priority Date: 03/17/2008
• Status: Expired due to Fees

• Current Assignee: Ensurge Micropower ASA
• Original Assignee: Kovio Incorporated (Ensurge Micropower ASA)
• Inventors: Li, Jiang
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US12/405,909
• Time in Patent Office: 1,036 Days
• Field of Search: 716/100, 716/118, 716/119, 716/139
• US Class Current: 716/139
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H03K 19/17796 for physical disposition of blocks

Abstract

Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.

Claims

1. A method of field programming an integrated circuit comprising:

a) inputting logic and/or circuit functions into a computer configured to design and correct one or more field-configurable circuit layouts;

b) designing one or more circuit layouts from the logic and/or circuit functions; and

c) printing one or more metal layers on a transistor array on a substrate, the transistor array having a dielectric layer thereon, according to the one or more circuit layouts.

2. The method of claim 1, further comprising correcting the one or more circuit layouts, wherein said one or more metal layers are printed according to the corrected one or more circuit layouts.

3. The method of claim 2, wherein correcting the one or more circuit layouts comprises one or more processes including converting, resampling, and/or reprocessing the circuit layout to produce a working bitmap;

determining and applying a set of correction rules; and

/or manual manipulation of the circuit layout.

4. The method of claim 1, further comprising providing the one or more circuit layouts directly to a printing device.

5. The method of claim 1, wherein printing the one or more metal layers comprises inkjet printing, micro-spotting, pen-coating, syringe dispensing, pump dispensing, vapor-jet printing, gravure printing, offset lithography, flexographic printing, stamping, or screen printing an ink comprising a metal precursor in a solvent.

6. A method of field-configuring a circuit, comprising:

a) depositing a first metal ink according to a predetermined wiring pattern on or over a substrate having an array of transistors thereon and a first dielectric layer on the transistors, the first dielectric layer having a first plurality of contact openings therein exposing a surface of each terminal of the transistors, wherein the predetermined wiring pattern enables predetermined functionality and/or logic in a circuit comprising the transistors and the predetermined wiring pattern; and

b) forming a first plurality of patterned metal lines from the first metal ink.

7. The method of claim 6, comprising depositing the first metal ink in some or all of the first plurality of contact openings.

8. The method of claim 6, wherein the array of transistors comprises a plurality of rows and a plurality of columns, wherein each intersection of one row and one column defines a location of one transistor in the array.

9. The method of claim 6, wherein the substrate comprises a single crystal silicon wafer, a metal sheet, a metal foil, a plastic sheet, a plastic film, a plastic web, a glass sheet or a glass slip.

10. The method of claim 6, further comprising printing the first dielectric layer on the substrate.

11. The method of claim 10, further comprising forming the first plurality of contact openings in the first dielectric layer after printing the first dielectric layer, to expose the terminals of the transistors.

12. The method of claim 10, comprising selectively printing the first dielectric layer in a pattern covering portions of the transistors and exposing the terminals of the transistors.

13. The method of claim 10, wherein the first dielectric layer comprises an N- and/or P-dopant.

14. The method of claim 10, wherein depositing the first metal ink comprises printing the first metal ink.

15. The method of claim 14, wherein printing the first metal ink comprises inkjet printing, gravure printing, off-set lithography, screen printing, flexographic printing, microspotting, pen-coating, laser writing, syringe dispensing, stencil printing, and/or pump dispensing the metal ink.

16. The method of claim 6, wherein the first dielectric layer has a first layer of patterned metal wires thereon electrically connected to the terminals of the transistors in the array, and the substrate further comprises a second dielectric layer on the first layer of patterned metal wires having a second plurality of contact openings therein.

17. The method of claim 6, wherein the transistors comprise thin film transistors.

18. The method of claim 6, wherein the first metal ink comprises a metal precursor material and a solvent.

19. The method of claim 18, wherein the metal ink comprises the metal precursor material in an amount of 1 to 50 wt. % of the ink, and the metal precursor material is soluble in the solvent.

20. The method of claim 19, wherein the metal precursor material comprises a metal compound and/or metal nanoparticles.

21. The method of claim 20, wherein the metal precursor material comprises a metal compound of aluminum, titanium, vanadium, copper, silver, chromium, molybdenum, tungsten, cobalt, nickel, gold, palladium, platinum, zinc, and/or iron.

22. The method of claim 18, comprising drying the metal-containing ink to remove the solvent and form a dried metal-containing material, and annealing the dried metal-containing material to form the first plurality of patterned metal lines.

23. The method of claim 6, further comprising forming a second dielectric layer on the first plurality of patterned metal lines, the second dielectric layer having a second plurality of contact openings therein exposing portions of the first plurality of patterned metal lines, and printing a second metal ink on the second dielectric layer.

24. The method of claim 23, further comprising forming a second plurality of patterned metal lines from the printed second metal ink.

25. The method of claim 6, comprising curing the deposited first metal ink to form the first plurality of patterned metal lines.

26. The method of claim 6, wherein forming the first plurality of patterned metal lines comprises printing a seed layer and then forming a bulk conductive layer on the seed layer.

27. A device comprising:

a) a substrate with an array of transistors thereon;

b) a first dielectric layer on the substrate having a first plurality of contact openings therein, each contact opening exposing a transistor terminal;

c) a first layer of patterned metal wires electrically connected to the terminals of the transistors in the array;

d) a second dielectric layer on the first layer of patterned metal wires having a second plurality of contact openings therein, exposing a surface of the first layer of patterned metal wires; and

e) a first printed pattern of metal lines thereon or thereover.

28. The device of claim 27, wherein the array of transistors comprises a plurality of rows and a plurality of columns and wherein each intersection of one row and one column defines a location of one transistor in the array.

29. The device of claim 27, wherein the first printed pattern of metal lines fills some or all of the second plurality of contact openings.

30. The device of claim 27, wherein the first printed pattern of metal lines comprises a seed layer and a bulk conductive layer.

31. The device of claim 27, further comprising a second layer of patterned metal wires on the second dielectric layer, and a third dielectric layer on the second layer of patterned metal wires.

32. The device of claim 31, wherein the third dielectric layer has a third plurality of contact openings therein.

33. The device of claim 27, wherein the substrate comprises a single crystal silicon wafer, a metal sheet, a metal foil, a plastic sheet, a plastic film, a plastic web, a glass sheet or a glass slip.

34. The device of claim 27, further comprising one or more capacitors, diodes, and/or inductors on the substrate, wherein at least one of the first layer of patterned metal wires and the first printed pattern of metal lines electrically connects at least one of the plurality of transistors to at least one of the one or more capacitors, diodes, and/or inductors.

35. The device of claim 27, wherein the first layer of patterned metal wires is printed.