Generating a hardware description based on a diagram with states and state transitions

• US 8,099,712 B2
• Filed: 03/26/2009
• Issued: 01/17/2012
• Est. Priority Date: 12/20/2000
• Status: Expired due to Term

• Current Assignee: National Instruments Corporation (Emerson Electric Company)
• Original Assignee: National Instruments Corporation (Emerson Electric Company)
• Inventors: Kodosky, Jeffrey L., Hogan, Kevin
• Primary Examiner(s): Kang, Insun
• Application Number:
  US12/412,203
• Publication Number:
  US 20090235231A1
• Time in Patent Office: 1,027 Days
• Field of Search: None
• US Class Current: 717/109
• CPC Class Codes: G06F 8/10 Requirements analysis; Specification techniques
• CPC Class Codes: G06F 8/34 Graphical or visual programming

Abstract

A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.

Claims

1. A computer-accessible memory medium storing program instructions executable by a processor to:

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a data flow program based on the first diagram, wherein the data flow program specifies a plurality of nodes and interconnections between the nodes, and wherein the data flow program specifies the first functionality;

store the data flow program in a memory; and

automatically generate a hardware description based on the data flow program, wherein the hardware description specifies a hardware implementation of the data flow program, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

2. The memory medium of claim 1, wherein the data flow program is executable by a processor to perform the first functionality.

3. The memory medium of claim 1, wherein the program instructions are further executable to:

configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements the hardware implementation of the data flow program.

4. The memory medium of claim 1,

wherein, for at least one state of the one or more states, the first diagram comprises program code associated with the at least one state;

wherein the automatically generated data flow program comprises the specified program code.

5. The memory medium of claim 1,

wherein, for at least one state, the first diagram comprises program code associated with the state;

wherein the automatically generated data flow program is operable to invoke the specified program code.

6. The memory medium of claim 1,

wherein the automatically generated data flow program comprises at least one placeholder for at least one state transition of the one or more transitions.

7. The memory medium of claim 6, wherein the program instructions are further executable to:

for the one or more state transitions, receive user input specifying a Boolean condition associated with each state transition.

8. The memory medium of claim 1,

wherein the first diagram specifies at least two state transitions from a particular state;

wherein the first diagram also specifies a priority ordering for the at least two state transitions;

wherein said automatically generating comprises automatically generating the data flow program such that, during execution of the data flow program, conditions associated with the at least two state transitions are evaluated in the specified priority ordering.

9. The memory medium of claim 1, wherein a first portion of the data flow diagram comprises a graphical user interface (GUI) for providing input to the data flow diagram and displaying output from the data flow diagram, and wherein the program instructions are further executable to compile the first portion of the data flow diagram for execution on a processor to present the GUI on a display.

10. The memory medium of claim 9, wherein the program instructions are further executable to:

configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the data flow diagram;

execute the first portion of the data flow diagram on the processor to present the GUI on the display;

receive user input to the GUI; and

provide the user input to the configured programmable hardware element, wherein the configured programmable hardware element is operable to adjust operation in response to the user input to the GUI.

11. A method, comprising:

receiving a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generating a data flow program based on the first diagram, wherein the data flow program specifies a plurality of nodes and interconnections between the nodes, and wherein the data flow program specifies the first functionality;

storing the data flow program in a memory; and

automatically generating a hardware description based on the data flow program, wherein the hardware description specifies a hardware implementation of the data flow program, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

12. The method of claim 11, wherein the data flow program is executable by a processor to perform the first functionality.

13. The method of claim 11, further comprising:

configuring the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements the hardware implementation of the data flow program.

14. The method of claim 11,

wherein, for at least one state of the one or more states, the first diagram comprises program code associated with the at least one state;

wherein the automatically generated data flow program comprises the specified program code.

15. The method of claim 11,

wherein, for at least one state, the first diagram comprises program code associated with the state;

wherein the automatically generated data flow program is operable to invoke the specified program code.

16. The method of claim 11,

wherein the automatically generated data flow program comprises at least one placeholder for at least one state transition of the one or more transitions.

17. The method of claim 16, further comprising:

for the one or more state transitions, receiving user input specifying a Boolean condition associated with each state transition.

18. The method of claim 11,

wherein the first diagram specifies at least two state transitions from a particular state;

wherein the first diagram also specifies a priority ordering for the at least two state transitions;

wherein said automatically generating comprises automatically generating the data flow program such that, during execution of the data flow program, conditions associated with the at least two state transitions are evaluated in the specified priority ordering.

19. The method of claim 11, wherein a first portion of the data flow diagram comprises a graphical user interface (GUI) for providing input to the data flow diagram and displaying output from the data flow diagram, and wherein the method further comprises compiling the first portion of the data flow diagram for execution on a processor to present the GUI on a display.

20. The method of claim 19, further comprising:

configuring the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements a hardware implementation of the data flow diagram;

executing the first portion of the data flow diagram on the processor to present the GUI on the display;

receiving user input to the GUI; and

providing the user input to the configured programmable hardware element, wherein the configured programmable hardware element is operable to adjust operation in response to the user input to the GUI.

21. A system for generating a hardware description from diagram information, comprising:

a processor;

a memory medium coupled to the processor, wherein the memory medium comprises program instructions executable by the processor to;

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a data flow program based on the first diagram, wherein the data flow program specifies a plurality of nodes and interconnections between the nodes, and wherein the data flow program specifies the first functionality;

store the data flow program in a memory; and

automatically generate a hardware description based on the data flow program, wherein the hardware description specifies a hardware implementation of the data flow program, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

22. The system of claim 21, further comprising:

a programmable hardware element coupled to the processor and the memory medium;

wherein the program instructions are further executable to configure the programmable hardware element to produce a configured programmable hardware element, and wherein the configured programmable hardware element implements the hardware implementation of the data flow program.

23. A system, comprising:

means for receiving a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

means for automatically generating a data flow program based on the first diagram, wherein the data flow program specifies a plurality of nodes and interconnections between the nodes, and wherein the data flow program specifies the first functionality; and

means for generating a hardware description based on the data flow program, wherein the hardware description specifies a hardware implementation of the data flow program, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

24. A computer-accessible memory medium storing program instructions executable by a processor to:

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a representation based on the first diagram, wherein the representation specifies the first functionality;

automatically generate a data flow diagram based on the representation, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality;

and automatically generate a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

25. The memory medium of claim 24, wherein the first diagram comprises a high-level representation, and wherein the representation comprises an intermediate representation.

26. The memory medium of claim 24, wherein the plurality of nodes comprises at least one structure node, wherein the structure node represents control flow of data among one or more of the plurality of nodes.

27. The memory medium of claim 24, wherein the program instructions are further executable to:

configure the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements the hardware implementation of the data flow diagram.

28. The memory medium of claim 24, wherein, for at least one state of the one or more states, the first diagram comprises program code associated with the at least one state;

wherein the automatically generated data flow diagram comprises the specified program code.

29. The memory medium of claim 24, wherein, for at least one state, the first diagram comprises program code associated with the state.

30. The memory medium of claim 24, wherein the automatically generated data flow diagram comprises at least one placeholder for at least one state transition of the one or more transitions, wherein the program instructions are further executable to:

for the one or more state transitions, receive user input specifying a Boolean condition associated with each state transition.

31. The memory medium of claim 24, wherein the first diagram specifies at least two state transitions from a particular state;

wherein the first diagram also specifies a priority ordering for the at least two state transitions;

wherein the data flow diagram specifies the at least two state transitions and the priority ordering for the at least two state transitions.

32. A method, comprising:

receiving a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generating a representation based on the first diagram, wherein the representation specifies the first functionality;

automatically generating a data flow diagram based on the representation, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality;

and automatically generating a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

33. The method of claim 32, wherein the first diagram comprises a high-level representation, and wherein the representation comprises an intermediate representation.

34. The method of claim 32, wherein the plurality of nodes comprises at least one structure node, wherein the structure node represents control flow of data among one or more of the plurality of nodes.

35. The method of claim 32, further comprising:

configuring the programmable hardware element utilizing the hardware description to produce a configured hardware element, wherein the configured hardware element implements the hardware implementation of the data flow diagram.

36. The method of claim 32, wherein, for at least one state of the one or more states, the first diagram comprises program code associated with the at least one state;

wherein the automatically generated data flow diagram comprises the specified program code.

37. The method of claim 32, wherein, for at least one state, the first diagram comprises program code associated with the state.

38. The method of claim 32, wherein the automatically generated data flow diagram comprises at least one placeholder for at least one state transition of the one or more transitions, wherein the method further comprises:

for the one or more state transitions, receiving user input specifying a Boolean condition associated with each state transition.

39. The method of claim 32, wherein the first diagram specifies at least two state transitions from a particular state;

wherein the first diagram also specifies a priority ordering for the at least two state transitions;

wherein the data flow diagram specifies the at least two state transitions and the priority ordering for the at least two state transitions.

40. A system for generating a hardware description from diagram information, comprising:

a processor;

a memory medium coupled to the processor, wherein the memory medium comprises program instructions executable by the processor to;

receive a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

automatically generate a representation based on the first diagram, wherein the representation specifies the first functionality;

automatically generate a data flow diagram based on the representation, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality;

and automatically generate a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.

41. The system of claim 40, further comprising:

a programmable hardware element coupled to the processor and the memory medium;

wherein the program instructions are further executable to configure the programmable hardware element to produce a configured programmable hardware element, and wherein the configured programmable hardware element implements the hardware implementation of the data flow diagram.

42. A system, comprising:

means for receiving a first diagram, wherein the first diagram specifies one or more states and one or more transitions between the states, wherein the first diagram specifies first functionality;

means for automatically generating a representation based on the first diagram, wherein the representation specifies the first functionality;

means for automatically generating a data flow diagram based on the representation, wherein the data flow diagram comprises a plurality of nodes and connections between the nodes, wherein the data flow diagram specifies the first functionality; and

means for automatically generating a hardware description based on the data flow diagram, wherein the hardware description specifies a hardware implementation of the data flow diagram, and wherein the hardware description is usable to configure a programmable hardware element to implement the first functionality.