Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures
First Claim
1. A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:
- providing a semiconductor substrate selected from pre fabricated CMOS circuits, MEMS and NEMS materials on a front side and a polished backside area available for post-CMOS, micro/nano fabrication with through substrate conductive vias and the prefabricated MEMS or NEMS materials having conductive structural and dielectric layers;
forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side;
applying at least one filler material in the at least one opening on the semiconductor substrate;
positioning at least one prefabricated MEMS, NEMS or CMOS chip on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate;
forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip;
performing at least one micro/nano fabrication etching step to release the MEMS/NEMS structural layer on the front side.
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Abstract
A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips.
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Citations
15 Claims
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1. A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:
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providing a semiconductor substrate selected from pre fabricated CMOS circuits, MEMS and NEMS materials on a front side and a polished backside area available for post-CMOS, micro/nano fabrication with through substrate conductive vias and the prefabricated MEMS or NEMS materials having conductive structural and dielectric layers; forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated MEMS, NEMS or CMOS chip on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate; forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip; performing at least one micro/nano fabrication etching step to release the MEMS/NEMS structural layer on the front side. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:
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providing a semiconductor substrate with pre-fabricated CMOS circuits on a front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate including protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one MEMS, NEMS chips with pre-fabricated structural and dielectric layers or CMOS chips on the filler material, the chip including a front face and a bare back face with the filler material enabling planarization of all the corners of the chip to the substrate; forming at least one metallization layer connecting the through substrate conductive vias to the at least one chip; performing at least one micro/nano fabrication etching step to release the structural on the prefabricated MEMS/NEMS chips; positioning a protective cap to package the integrated device over the MEMS/NEMS device area on the pre-fabricated chips. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification