Method of forming monolithic CMOS-MEMS hybrid integrated, packaged structures

• US 8,101,469 B2
• Filed: 03/26/2010
• Issued: 01/24/2012
• Est. Priority Date: 07/02/2009
• Status: Expired due to Fees

• Current Assignee: AMF-Nano Corporation
• Original Assignee: Advanced Microfab, LLC
• Inventors: Kumar, G. Krishna, Choksi, Nishit A., Chalil, Joseph M.
• Primary Examiner(s): Le, Dung A.
• Application Number:
  US12/732,689
• Publication Number:
  US 20110003421A1
• Time in Patent Office: 669 Days
• Field of Search: 438 25- 26, 438/33, 438/51, 438/55, 438106-127, 257/676
• US Class Current: 438/123
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00238 Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01027 Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/16235 : Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip
• CPC Class Codes: H01L 2924/167 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2924/16788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/1679 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate.

Claims

1. A method of forming a Monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:

providing a semiconductor substrate;

applying at least one first insulating layer that is temperature independent to the semiconductor substrate with at least a portion of the first insulating layer being a sacrificial layer;

applying at least one structural layer that is temperature independent to the first insulating layer with at least a portion of the structural layer being made conductive;

patterning the structural layer and the insulating layer;

applying at least one protective layer overlying both the patterned first insulating and structural layer;

etching the first insulating and structural layer;

forming at least one opening in the semiconductor substrate and the protective layer;

applying at least one filler layer in the at least one opening on the semiconductor substrate;

positioning at least one chip on the filler layer, the chip including a front face and a back face;

applying at least one planarization layer overlying the substrate and the chip;

forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and a portion of a mechanical layer that is conductive on the substrate;

applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one chip;

applying at least one second insulating layer overlying the metallization layer;

performing at least one micro/nano fabrication etching step with at least a portion of the first insulating layer that is the sacrificial layer.

2. The method of claim 1, wherein the mechanical layer comprises polysilicon with the portion of the conductive area being doped and annealed.

3. The method of claim 1, wherein the first insulating layer comprises high temperature, 1000 degrees Centigrade or more deposited silicon-dioxide.

4. The method of claim 1, wherein the protective layer comprises Photoresist.

5. The method of claim 1, wherein the opening in the semiconductor substrate is formed by etching with Deep Reactive Ion Etching (DRIE).

6. The method of claim 1, wherein the filler layer is epoxy.

7. The method of claim 1, wherein the filler layer is selected from photo patternable materials including SU8, and PDMS.

8. The method of claim 1, wherein the at least one chip is selected from:

CMOS integrated circuits, electronics, amplifier dies, analog to digital converters or diced chips from another MEMS/NEMS fabrication process.

9. The method of claim 1, wherein the planarization layer is selected from oxides, nitrides, glass, quartz, and polymers.

10. The method of claim 1, wherein the metallization layer is selected from aluminum, titanium, chrome, gold or platinum or a combination of the same that can be evaporated, sputtered or electroplated.

11. The method of claim 1, wherein the second insulating layer is selected from oxides, nitrides, glass, quartz, and polymers.

12. The method of claim 1, wherein the micro/nano fabrication etching step is selected from wet, dry, isotropic, and anisotropic etching.

13. The method of claim 1, wherein the micro/nano fabrication etching further comprises surface micromachining, bulk micromachining, dry etching, and chemical etching from a backside of the substrate.

14. A method of forming monolithic CMOS-MEMS hybrid integrated, packaged device comprising the steps of:

providing a semiconductor substrate;

forming at least one portion of the semiconductor substrate to contain a patterned MEMS/NEMS sensing area comprising at least one first insulating layer that is temperature independent and at least one temperature independent structural layer with at least one portion being made conductive;

attaching at least one IC/CMOS die in close proximity to the sensing area by positioning it into at least one opening formed through a portion of the semiconductor substrate by etching away the first insulating and structural layer;

applying at least one planarization layer overlying the substrate, and the IC/CMOS die;

forming at least one via opening on a portion of the planarization layer interfacing IC/CMOS die and a portion of a mechanical layer that is conductive on the substrate;

applying at least one metallization layer overlying the planarization layer connecting the metallization layer on the substrate to the IC/CMOS die;

applying at least one second insulating layer overlying the metallization layer.

15. The method of claim 14, wherein the mechanical layer comprises polysilicon with the portion of the conductive area being doped and annealed.

16. The method of claim 14, wherein the first insulating layer comprises high temperature, 1000 degrees Centigrade or more deposited silicon-dioxide.

17. The method of claim 14, wherein the opening in the semiconductor substrate is formed by etching with Deep Reactive Ion Etching (DRIE).

18. The method of claim 14, wherein the at least one IC/CMOS die is selected from:

CMOS integrated circuits, electronics, amplifier dies, Analog to Digital converters, or diced chips from another MEMS/NEMS fabrication process.

19. The method of claim 14, wherein the planarization layer is selected from oxides, nitrides, glass, quartz, and polymers.

20. The method of claim 14, wherein the metallization layer is selected from aluminum, titanium, chrome, gold or platinum or a combination of the same that can be evaporated, sputtered or electroplated.

21. The method of claim 14, wherein the second insulating layer is selected from oxides, nitrides, glass, quartz, and polymers.