Method of forming a FET having ultra-low on-resistance and low gate charge

• US 8,101,484 B2
• Filed: 06/23/2010
• Issued: 01/24/2012
• Est. Priority Date: 08/16/2000
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Bencuya, Izak, Mo, Brian Sze-Ki, Challa, Ashok
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): Garcia, Joannie A
• Application Number:
  US12/821,590
• Publication Number:
  US 20100258864A1
• Time in Patent Office: 580 Days
• Field of Search: 438/156, 438/212, 438/268, 438/269, 438/270, 438/272, 438/FOR.192, 438/FOR.176, 257/328, 257/329, 257/330, 257/331, 257/334
• US Class Current: 438/270
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Claims

1. A method of forming a field effect transistor, comprising:

providing a substrate of a first conductivity type silicon;

forming a substrate cap region of the first conductivity type silicon such that a junction is formed between the substrate cap region and the substrate;

forming a body region of a second conductivity type silicon such that a junction is formed between the body region and the substrate cap region;

forming a trench extending through at least the body region; and

forming a source region of the first conductivity type in an upper portion of the body region,

wherein during one or more temperature cycles, dopants of the first conductivity type in the substrate cap region out-diffuse into a lower portion of the body region to thereby form an out-diffusion region of the first conductivity type in the lower portion of the body region such that a spacing between the source region and the substrate out-diffusion region defines a length of a channel region of the field effect transistor.

2. The method of claim 1 further comprising:

lining the sidewalls and bottom of the trench with a dielectric material; and

at least partially filling the trench with a conductive material.

3. The method of claim 2 wherein:

the trench further extends through the out-diffusion region and the substrate cap region, and

the conductive material extends through a substantial depth of the out-diffusion region.

4. The method of claim 2 wherein the dielectric material is thicker along the bottom of the trench than along its sidewalls.

5. The method of claim 2 further comprising:

forming a dielectric plug along the bottom of the trench so that the trench has a thicker dielectric material along its bottom than along its sidewalls.

6. The method of claim 5 wherein the dielectric plug is formed using one of high density plasma chemical vapor deposition and sub-atmospheric chemical vapor deposition.

7. The method of claim 1 wherein the substrate cap region has a resistivity which varies less than a resistivity of the substrate.

8. The method of claim 1 wherein the out-diffusion region extends from an interface between the body region and the substrate cap region into the body region.

9. The method of claim 1 wherein during the one or more temperature cycles the substrate cap region influences said out-diffusion of the dopants of the first conductivity type into the body region such that the length of the channel region varies less and thus is substantially predictable.

10. The method of claim 1 wherein the substrate cap region and the body region are epitaxially formed.

11. The method of claim 1 wherein the out-diffusion region has a graded doping concentration decreasing in a direction away from an interface between the out-diffusion region and the substrate cap region.

12. The method of claim 1 wherein the substrate cap region has a lower doping concentration than a doping concentration of the substrate.

13. The method of claim 1 wherein the trench extends partially into the substrate.

14. The method of claim 1 wherein the substrate cap region has a thickness of less than or equal to two micrometers.

15. The method of claim 1 further comprising:

forming an epitaxial layer of the first conductivity type silicon over and in contact with the substrate cap region, wherein the body region is formed by implanting dopants of the second conductivity type into the epitaxial layer and driving the dopants into the epitaxial layer so that the body region forms a junction with the substrate cap region.

16. The method of claim 15 wherein the substrate cap region is epitaxially formed over and in contact with the substrate.

17. The method of claim 15 wherein the substrate cap region is formed in the substrate by implanting dopants of the first conductivity type into the substrate.

18. A field effect transistor, comprising:

a substrate of a first conductivity type silicon;

a substrate cap region of the first conductivity type silicon forming a junction with the substrate;

a body region of a second conductivity type silicon over and in contact with the substrate cap region;

a trench extending at least through the body region;

a source region of the first conductivity type formed in an upper portion of the body region; and

an out-diffusion region of the first conductivity type formed in a lower portion of the body region such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

19. The field effect transistor of claim 18 further comprising:

a dielectric material lining the sidewalls and bottom of the trench; and

a conductive material at least partially filling the trench.

20. The field effect transistor of claim 18 wherein:

the trench further extends through the out-diffusion region and the substrate cap region, and

the conductive material in the trench extends through a substantial depth of the out-diffusion region.

21. The field effect transistor of claim 18 wherein the dielectric material is thicker along the bottom of the trench than along its sidewalls.

22. The field effect transistor of claim 18 wherein the out-diffusion region extends from an interface between the body region and the substrate cap region into the body region.

23. The field effect transistor of claim 18 wherein the substrate out-diffusion region is formed as a result of dopants out-diffusing from the substrate cap region into the body region.

24. The field effect transistor of claim 18 wherein the substrate cap region and the body region are epitaxial layers.

25. The field effect transistor of claim 18 wherein the out-diffusion region has a graded doping concentration decreasing in a direction away from an interface between the out-diffusion region and the substrate cap region.

26. The field effect transistor of claim 18 wherein the substrate cap region has a lower doping concentration than a doping concentration of the substrate.

27. The field effect transistor of claim 18 wherein the trench extends partially into the substrate.

28. The field effect transistor of claim 18 wherein the substrate cap region has a thickness of less than or equal to two micrometers.

29. The method of claim 18 wherein the substrate cap region is an epitaxial layer.

30. The method of claim 18 wherein the substrate cap region is a diffusion region within the substrate.