Method of and system for implementing a circuit in a device having programmable logic

• US 8,102,188 B1
• Filed: 04/09/2010
• Issued: 01/24/2012
• Est. Priority Date: 01/11/2008
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Chan, Chi Bun, Shirazi, Nabeel
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): Tran, Thienvu
• Application Number:
  US12/757,770
• Time in Patent Office: 655 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/38
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory is disclosed. The method comprises configuring the programmable resources of the device with a circuit design; storing a first page of data in a block of random access memory; determining a page fault while interfacing with the block of random access memory when implementing the circuit design; performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and accessing the second page of data. A system of implementing a circuit in a device having programmable logic is also disclosed.

Claims

1. A method of implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory, the method comprising:

configuring the programmable resources of the device with a circuit design;

storing a first page of data in a block of random access memory;

wherein the first page of data comprises a segment of a partitioned address space;

determining a page fault while interfacing with the block of random access memory when implementing the circuit design, wherein the page fault indicates a request to access a page of data that does not reside on the block of random access memory;

performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory;

wherein the second page of data comprises another segment of another partitioned address space; and

accessing the second page of data.

2. The method of claim 1 further comprising coupling a page fault signal to a write enable input of the block of random access memory after determining a page fault.

3. The method of claim 1 further comprising coupling an address from the circuit design to the block of random access memory.

4. The method of claim 3 wherein coupling an address from the circuit design to the block of random access memory comprises coupling a first portion of the address to the block of random access memory and a second portion of the address to a page index comparator.

5. The method of claim 1 further comprising selecting the content of a feed forward register after a page fault is detected when reading data from the block of random access memory.

6. The method of claim 1 wherein performing a partial reconfiguration comprises reconfiguring data in the block of random access memory by way of a reconfiguration port.

7. The method of claim 1 further comprising disabling the clock signal to the block of random access memory when performing a partial reconfiguration of the device.

8. A system for implementing a circuit in a device having programmable resources and a predetermined amount of available internal memory, the system comprising:

means for configuring the programmable resources of the device with a circuit design;

means for storing a first page of data in a block of random access memory;

means for determining a page fault while interfacing with the block of random access memory when implementing the circuit design;

means for performing a partial reconfiguration of the device, wherein a second page of data is stored in the block of random access memory; and

means for accessing the second page of data.